Arria II GX Devices Family Overview

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1–8 Chapter 1: Arria II GX Device Family OverviewArria II GX Device ArchitectureTable 1–5 lists the Arria II GX device memory modes.Table 1–5. Memory Modes for Arria II GX DevicesPort ModePort Width ConfigurationSingle Port ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36Simple Dual Port ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36True Dual Port ×1, ×2, ×4, ×8, ×9, ×16, and ×18DSP ResourcesI/O Features■■■■■■Fulfills the DSP requirements of 3G and Long Term Evolution (LTE) wirelessinfrastructure applications, video processing applications, and voice processingapplicationsDSP block input registers efficiently implement shift registers for finite impulseresponse (FIR) filter applicationsThe Quartus II software includes megafunctions you can use to control the modeof operation of the DSP blocks based on user-parameter settingsYou can directly infer multipliers from the VHDL or Verilog HDL source codeContains up to 12 modular I/O banksAll I/O banks support a wide range of single-ended and differential I/Ostandards, as listed in Table 1–6Table 1–6. I/O Standards Support for Arria II GX DevicesTypeSingle-Ended I/ODifferential I/OI/O StandardLVTTL, LVCMOS, SSTL, HSTL, PCIe, and PCI-XSSTL, HSTL, LVPECL, LVDS, mini-LVDS, Bus LVDS (BLVDS), and RSDS■■■■Supports programmable bus hold, programmable weak pull-up resistors, andprogrammable slew rate controlCalibrates OCT or driver impedance matching for single-ended I/O standardswith one OCT calibration block on the top-left, top-right, and bottom-left cornersof the deviceDedicated configuration banks at Bank 3C and 8C which support dedicatedconfiguration pins and some of the dual-purpose pins with a configurationscheme at 1.8, 2.5, 3.0, and 3.3 VDedicated VREF pin per I/O bank to allow voltage-referenced I/O standards. EachI/O bank can operate at independent V CCIO and V REF levelsArria II GX Device Handbook, Volume 1 © July 2010 Altera Corporation
Chapter 1: Arria II GX Device Family Overview 1–9Arria II GX Device ArchitectureHigh-Speed LVDS I/O and DPA■■■■Clock Management■■■Dedicated circuitry for implementing LVDS interfaces at speeds from 150 Mbps to1.25 GbpsR D OCT for high-speed LVDS interfacingDPA circuitry and soft-CDR circuitry at the receiver automatically compensates forchannel-to-channel and channel-to-clock skew in source-synchronous interfacesand allows for implementation of asynchronous serial interfaces with embeddedclocks at data rates from 150 Mbps to 1.25 GbpsEmulated LVDS output buffers use two single-ended output buffers with anexternal resistor network to support LVDS, mini-LVDS, BLVDS, and RSDSstandards.Provides dedicated global clock networks (GCLKs), regional clock networks(RCLKs), and periphery clock networks (PCLKs) that are organized into ahierarchical structure that provides up to 148 unique clock domainsUp to six PLLs with seven outputs per PLL to provide robust clock managementand synthesis■■■Independently programmable PLL outputs, creating a unique andcustomizable clock frequency with no fixed relation to any other clockInherent jitter filtration and fine granularity control over multiply and divideratiosSupports spread-spectrum input clocking and counter cascading with PLLinput clock frequencies ranging from 5 to 500 MHz to support both low-costand high-end clock performanceFPGA fabric can use the unused transceiver PLLs to provide more flexibilityAuto-Calibrating External Memory Interfaces■■■I/O structure enhanced to provide flexible and cost-effective support for differenttypes of memory interfacesContains features such as OCT and DQ/DQS pin groupings to enable rapid androbust implementation of different memory standardsAn auto-calibrating megafunction is available in the Quartus II software forDDR SDRAM, DDR2 SDRAM, and DDR3 SDRAM memory interface PHYs; themegafunction takes advantage of the PLL dynamic reconfiguration feature tocalibrate based on the changes of process, voltage, and temperature (PVT).© July 2010 Altera Corporation Arria II GX Device Handbook, Volume 1
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