Increased Rate of Multiple-Bit Upset at Large Angles of Incidence
Increased Rate of Multiple-Bit Upset at Large Angles of Incidence
Increased Rate of Multiple-Bit Upset at Large Angles of Incidence
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BackgroundExperimentalModelingSummaryDevice under test is a TI 90 nm SRAMTI 90nm CMOS high performance (C027)DSP embedded SRAM (8MEG) @ 1.2 VLANL WNR Neutron beam lineDevice under testSingle-bit<strong>Multiple</strong>-bitMultiplicityTest conditions - 0°, 45°, 90°, & 180°Alan Douglas TiptonNASA Review5
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