Burr Brown PCM1738 - 24-Bit, 192kHz Sampling.pdf - MaxDat

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ANALOG FIR FILTER PERFORMANCE FOR DSD MODE (Cont.)All specifications at T A = +25°C, V DD = +3.3V, V CC = +5V, SCKI = 11.2896MHz (44.1kHz • 256fS), and 50% modulation DSD data input, unless otherwise noted.0DSD FILTER 40DSD FILTER 4–1–20Gain (dB)–2–3–4Gain (dB)–40–60–5–80–60 50 100 150 200Frequency (kHz)–1000 500 1000 1500Frequency (kHz)10PCM1738SBAS174A
SYSTEM CLOCK AND RESETFUNCTIONSSYSTEM CLOCK INPUTThe PCM1738 requires a system clock for operating thedigital interpolation filters and advanced segment DACmodulators. The system clock is applied at the SCKI input(pin 7). The PCM1738 has a system-clock detection circuitthat automatically senses if the system clock is operating at128f S to 768f S . Table I shows examples of system-clockfrequencies for common audio sampling rates.Figure 1 shows the timing requirements for the system clockinput. For optimal performance, it is important to use a clocksource with low phase jitter and noise. The PLL1700 multiclockgenerator is an excellent choice for providing thePCM1738 system clock.SYSTEM CLOCK OUTPUTA buffered version of the system clock input is available atthe SCKO output (pin 10). SCKO can operate at either full(f SCKI ) or half (f SCKI /2) rate. The SCKO output frequencymay be programmed using the CLKD bit of Control Register19. The SCKO output pin can also be enabled or disabledusing the CLKE bit of Control Register 19. The default isSCKO enabled.POWER-ON AND EXTERNAL RESET FUNCTIONSThe PCM1738 includes a power-on reset function (seeFigure 2). The system clock input at SCKI should be activefor at least one clock period prior to V DD = 2.0V. With thesystem clock active, and V DD > 2.0V, the power-on resetfunction will be enabled. The initialization sequence requires1024 system clocks from the time V DD > 2.0V. Afterthe initialization period, the PCM1738 will be set to its resetdefault state, as described in the Mode Control Registersection of this data sheet.The PCM1738 also includes an external reset capabilityusing the RST input (pin 1). This allows an external controlleror master reset circuit to force the PCM1738 to initializeto its reset default state.See Figure 3 for external reset operation and timing. TheRST pin is set to a logic “0” for a minimum of 20ns. TheRST pin is then set to a logic “1” state that starts theinitialization sequence that requires 1024 system clock periods.After the initialization sequence is complete, thePCM1738 will be set to its reset default state, as describedin the Mode Control Register section of this data sheet.The external reset is especially useful in applications wherethere is a delay between the PCM1738 power-up and systemclock activation. In this case, the RST pin should be held ata logic “0” level until the system clock has been activated.The RST pin may then be set to a logic “1” state to start theinitialization sequence.SYSTEM CLOCK FREQUENCY (f SCLK ) (MHz)SAMPLINGFREQUENCY 128f S 192f S 256f S 384f S 512f S 768f S32kHz 4.0960 6.1440 8.1920 12.2880 16.3840 24.576044.1kHz 5.6488 8.4672 11.2896 16.9344 22.5792 33.868848kHz 6.1440 9.2160 12.2880 18.4320 24.5760 36.864096kHz 12.2880 18.4320 24.5760 36.8640 49.1520 73.7280192kHz 24.5760 36.8640 49.1520 73.7280 See Note (1) See Note (1)NOTE: (1) This system clock is not supported for the given sampling frequency.TABLE I. System Clock Rates for Common Audio Sampling Frequencies.t SCKHSystem Clock“H”“L”2.0V0.8Vt SCKLSystem clock pulsecycle time (1)System Clock Pulse Width HIGH t SCKH: 7ns (min)System Clock Pulse Width LOW t SCKL : 7ns (min)FIGURE 1. System Clock Input Timing.PCM1738 11SBAS174A
Page 2 and 3: SPECIFICATIONSAll specifications at
Page 4 and 5: V CC 1BLOCK DIAGRAMLRCKDATABCKInput
Page 6 and 7: TYPICAL PERFORMANCE CURVES (Cont.)A
Page 8 and 9: TYPICAL PERFORMANCE CURVES (Cont.)A
Page 12 and 13: t RSTReset Reset RemovalV DD2.4V/ma
Page 14 and 15: LRCK50% of V DDt BCH t BCL t LBBCK5
Page 16 and 17: MODE CONTROL REGISTERSUser-Programm
Page 18 and 19: REGISTER 18 (Cont.)FMT[2:0] Audio I
Page 20 and 21: REGISTER 19 (Cont.)FLTDigital Filte
Page 22 and 23: B15 B14 B13 B12 B11 B10 B9 B8 B7 B6
Page 24 and 25: APPLICATION FOR EXTERNAL DIGITAL FI
Page 26 and 27: APPLICATION FOR DSD FORMAT (DSD MOD
Page 28 and 29: APPLICATION FOR MONAURAL MODE OPERA
Page 30 and 31: CONSIDERATIONS FORAPPLICATIONS CIRC
Page 32: IMPORTANT NOTICETexas Instruments a

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