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SSI 73M291 0/291 OAMicrocontrollerREGISTER DESCRIPTION (continued)EXTERNAL INTERRUPT DIRECTION REGISTER (lDIR) SFR ADDRESS 92Byte AddressableReset State OOhBIT7 BIT6 BIT5 BIT4 BIT3 BIT20 0 INT2 INT1 INTO INTD2BIT 1INTD1BITOINTDOThese bits determine the polarity of the corresponding external signals INT(2:0) which will result in an interruptand will also allow the user to directly read the logic level at the pads INT(2:0).BITS(5:3) INT(2 :0)BITS(5:3) are read only bits that reflect the logic value at the corresponding pin. The value is not affected byBITS(2:0).BITS(2:0) Interrupt Polarity ControlIf the bit is set to a 0, a falling edge will trigger the interrupt. If the bit is set to a 1 , a rising edge will trigger theinterrupt. Also, if the bit is set to a 1, level generated interrupts will occur when the corresponding pin is high andthe internal pin signal to the timer controls will be inverted.Bits 6 and 7 will always be read as O's.CLOCK CONTROL REGISTER SFR ADDRESS DAByte AddressableReset State OOhBIT7 BIT6 BIT5 BIT4Activity CLK1 MCLK CLK2ENCTRL1 CTRLBIT3 BIT2 BIT 1 BITOCLK2 CLK2 CLK1EN CLK1CTRL1 CTRLO CTRLOThese bits determine the behavior at the CLK1 OUT and CLK20UT pins and allow the user to divide the maininternal processor clock frequency by two for power conservation.BIT7BIT 7 is an activity bit. It is cleared by a read of this register. If the activity bit is set it will prevent the 73M291 0from entering Sleep mode.BIT6When BIT 6 = 1, CLK10UT will be OSC/1.5 if bit 1 is a 1 and bit 0 is O.BIT5CLOCK OUT0 OSC1 OSC/2BIT 5 Master Clock ControlWhen BIT 5 is set to a 1 the internal processor clock is the oscillator frequency divided by 2. If this bit is a 0, theprocessor clock is the same frequency as the oscillator's.4-14