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:.4 DLCR3· Receive Interrupt Enable Reg isterThis register contains the bits to enable the status bits in DLCR1 to generate interrupts to the host.31T SYMBOL L DESCRIPTION7 PKT_RDY R,W,O PKT_RDY INTERRUPT ENABLE: When this bit is set high, it will enable PKT_RDYINT ENABLE(Packet Ready signal) to generate an interrupt.6 HRD_ERR R,W,O HRD_ERR INTERRUPT ENABLE: When high, enables HRD_ERR (Host Read Error)INT ENABLEto generate an interrupt.5 DMA_EOP R,W,O DMA_EOP INTERRUPT ENABLE: When high, enables the DMA_EOP to generate anINT ENABLEinterrupt.4 RMTRST R,W,O RMTRST INTERRUPT ENABLE: When high, allows the- RMTRST (Remote ResetINT ENABLEPacket Received) to generate an interrupt.3 SRT_ERR R,W,O SRT_ERR INTERRUPT ENABLE: When high, enables SRT_ERR (Received ShortINT ENABLEPacket) to generate an interrupt.2 ALG_ERR R,W,O ALG_ERR INTERRUPT ENABLE: When high, enables ALG_ERR (Alignment Error) toINT ENABLEgenerate an interrupt.1 CRC_ERR R,W,O CRC_ERR INTERRUPT ENABLE: When high, enables--CRC_ERR to generate anINT ENABLEinterrupt.OVRFLO R,W,O OVRFLO INTERRUPT ENABLE: When high, enables OVRFLO (Receive Buffer OverINT ENABLEflow) flag to generate an interrupt.°2.5 DLCR4· Transmit Mode RegisterThis register contains the collision count value (up to 16 collisions). SSI 78Q8373 will attempt to fe-transmit the current packet upto 16 times. After which, depending on the values setting in BMR 11, the host can either skip the current packet and continueto transmit remaining packets in the transmit buffer or re-transmit the current packet again.BIT7-4321°SYMBOL L DESCRIPTIONCOL3-0 R,O COLLISION COUNT: These 4 bits store the collision counter value. Bit 3 is the mostsignificant bit of the count.NO_BACK R,W,O NO BACKOFF ENABLE: When set to 1, it will disable the binary exponential backoffcircuitry.NOT_CB R,W,1 NOT_CONTROL BIT: The inverse of this bit is available for general use on th CB pin.EDLOOP R,W,1 ENDEC LOOP BACK: Active low. This bit enables the-loop back function of the78Q8370-ENDEC. Loop back is active when this bit is set to '0'.DSC R,W,O DISREGARD CARRIER: Program this bit to zero for normal network operation. Whenset to high, the transmitter will not defer to traffic on the network.I9-51