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SSI78Q83733V, 5V PCMCIAEthernet ComboTABLE 6: Write Cycle, Generic Bus Mode (Refer to Figure 7)PARAMETERCS low to WR low;HA[O :3] valid to WR low t,WR high to CS high;WR high to HA[0:3] invalidt2CONDITIONSWR low pulse width t3 Vdd = 5VVdd = 3.3VWR low to READY low t4 (a) Vdd = 5VWR low to READY high (') ts (a)WR low to READY low (1) ts (b)WR high to READY high t7 (b)Vdd = 3.3VWR low to READY low ta (d) Vdd = 5VWR high to READY high t9 (d)HD[0:15] valid to WR high(data setup)t,oWR high to HD[0:15] invalid(data hold) t"Vdd = 3.3VMIN NOM MAX UNIT0 ns0 ns30 ns35 ns0 35 ns45 ns350 ns0 350 ns28 ns0 30 ns40 ns0 25 ns15 ns10 nsNote:(1) Maximum of 350 ns may occur if system makes contiguous system read cycles at less than100 ns intervals, and both the transmitter and receiver are active on "Ioopback" reception (if thetransmitter and receiver are idle, the max value becomes 250 ns). 2.4lls max for host write error.(a) For Buffer Memory Port when port is busy and RDYSEL = 1.(b) For Buffer Memory Port when port is busy and RDYSEL = O.(c) For register or port is not busy and RDYSEL = 1.(d) For register or port is not busy and RDYSEL = O.7-42