Actel FPGAs - MSC Budapest Kft.

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In-System ProgrammingSecure On-the-Fly ReprogrammabilityAn extremely important consideration is the extent to which the FPGA program can be configured safely in situ – with in-systemprogramming (ISP) that enables system designers and their customers to continue adding features and benefits to the systemthroughout its working life. Actel Fusion, IGLOO/e, and ProASIC3/E devices provide a complete solution for intellectual propertyand programming security that includes the following:A Secure Foundation because flash FPGAs are nonvolatile, live at power-up, andsinglechip, providing nonvolatile memory on-chip.FlashLock allows the designer to control the security levels of the array andFlashROM independently, including programming, verification, and encryption.Advanced Encryption (AES) is provided for the secure transmission of programmingfiles through the public domain.Message Authentication Control (MAC) is used in secure programming to verify thatprogramming information is not altered during transmission. The entire file can beauthenticated against device security settings before programming is initiated so thedevice retains its original information if the programming file is not valid.Nonvolatile Memory – FlashROM and Flash Memory Blocks (Fusion) the FPGAprovide storage for keys and identifiers to control the secure ISP and serializationprocesses, as well as sufficient space for user-defined data and applications.The above combination constitutes an in-system programming solution that issecure and provides key benefits to system designers and their customers. Thesepowerful features ensure that users of Actel Fusion, IGLOO/e, and ProASIC3/Edevices can protect their systems from harm in the form of overbuilding, device IP/design theft, product tampering, and other malicious activities.Live at Power-UpThe Time It Takes an FPGA to Power Up Has a Significant Impacton Effective System Design and Total System CostProgrammable logic devices based on nonvolatile memory technologies, such asActel flash and antifuse FPGAs, store their configuration in the logic gates. Thiseliminates the need to download the configuration, making these devices readilyavailable for operation in a similar way to standard semiconductor devices (ASICs/ASSPs). Other technologies, such as volatile SRAM-based programmable logicdevices, wake up in an unknown state and require the download of configurationfrom an external nonvolatile memory device during each power-up cycle. HybridSRAM devices have SRAM FPGA architecture and nonvolatile configuration memoryon-chip. These FPGAs must be loaded internally on each power-up cycle. Onlyafter the device is loaded with the configuration can it start operating according tothe customer application. After each power-down or brownout, the device loses itsconfiguration and needs to be loaded again in the next power-up cycle.Actel nonvolatile Level 0 live-at-power-up (LAPU) FPGAs speed initialization of systemcomponents and execute critical tasks up to 4,000 times sooner than SRAM or HybridFPGAs, and before the processor powers up and initializes. Critical tasks include setupand configuration of memory blocks, clock generation, synthesis and distribution, andbus activity management. The live-at-power-up capability of Actel nonvolatile devicesgreatly simplifies total system design and reduces total system cost. Using live-at-powerupActel FPGAs instead of SRAM or Hybrid FPGAs often eliminates the need for complexprogrammable logic devices (CPLDs), clock generation devices, and external PLLs.32
JTAG/Boundary Scan TestAffordable & Scriptable®Hpe ACT-Scanaffordable & scriptablen Cost efficient JTAG-ToolFor interactive board level debugging and production testsn IO-FilteringObserve IOs of interest onlyn Pin-File parsingUse your HDL top-level pin names to find signals quicklyn Scripting interfaceFor production tests and all repetitive tasksn Free with every Hpe ® _midi systemEvery Hpe ® _midi system comes with powerful andfree software tools, including Hpe ® _JTAGHave you ever attempted to measure signals between twoball grid arrays and then noticed that you forgot to insert testpads? Has the price of JTAG tools kept you from usingBoundary Scan Tests?With Hpe ® _JTAG Gleichmann Electronics Research introducesa cost efficient JTAG tool allowing you to debug and testyour PCBs and ICs. Hpe ® _JTAG gives the design engineer fullcontrol over the logical states of any I/O-pin or register thatis accessible via Boundary Scan at a fraction of the cost ofhigh-end JTAG tools. Opposed to most low-cost JTAG tools,Hpe ® _JTAG is fully scriptable, hence tests can be automatedfor production.IO-FilteringObserve IOs of interest only&Pin-File parsingUse your HDL top-level pinnames to find signals quicklyHpe ® _ACT-Scan will only allow Actel devices in theJTAG-chain. If a non-Actel device is in the JTAG-chain theuser has to upgrade to the Hpe ® _JTAG.Short description:Hpe ® _ACT-Scan is a tool for interactive PCB debugging.Hpe ® _ACT-Scan allows users to load pin names BSDL filesand/or from pin files generated during FPGA synthesis(*.rpt files).A powerful Python scripting interface allows users to automaterepetitive tasks and/or add functionality to the tool(for example to read out A/D register values for Actel FusionFPGAs).Demo version (Hpe ® _ACT-Scan Demo):Requires a license file that will be generated free of chargefor MSC customers only. The demo version will include:n A simulator (no real hardware required)n Support for Actel IGLOO AGL125V5Visit www.msc-toolguide.comto download your free demo software orfor ordering the Hpe ® _ACT-Scan Tool-SetRequest your demo license at act-licensing@msc-ge.comFor more information about the unrestrictedHpe ® _JTAG-Tool-Set please contact:Gleichmann Electronics Research (Austria)GmbH & Co KGSoftwarepark IT Center · Top 2/4AT - 4232 HagenbergTel. +43 7236 3351 4500sales@ge-research.comwww.ge-research.com33
Page 1 and 2: Actel FPGAsProduct Overview 2009Edi
Page 3 and 4: ProASIC ® 3 nanoThe Lowest Cost So
Page 5 and 6: ProASIC ® 3 for AutomotiveFrom Con
Page 7 and 8: IGLOO ® nanoThe Industry’s Lowes
Page 9 and 10: IGLOO ® Evaluation KitsStarting Yo
Page 11 and 12: Fusion Starter KitsStarting Your Fu
Page 13 and 14: Axcelerator Family of FPGAsHigh Per
Page 15 and 16: Real Time Verification/ProgrammingF
Page 17 and 18: Versa NetGlobalsInt.PLLincl. CCCSle
Page 19 and 20: Antifuse FPGA Selector GuideSystemG
Page 21 and 22: CSPTQFPCS289f IGLOO Plusps 14 x 14
Page 23 and 24: Secured by ActelActel FPGAs and Des
Page 25 and 26: FPGAs for Space ApplicationsA Histo
Page 27 and 28: Fusion in System ManagementThe Worl
Page 29 and 30: FPGA Development SoftwareActel’s
Page 31: Green PackagingThe Actel Commitment

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