TOOLS & SOFTWAREcomponent models to complete assembliesready for production – even newly created designelements are released to the vault so theycan be sourced back into a design. The benefitsof this defined and structured approach, basedaround managed vaults and advanced designdata management, are substantial and self-perpetuating.Design productivity ramps up asmore design content is created, released to andsubsequently approved for reuse from the vault.Future designs become quicker to implementas the vault-based repository of design buildingblocks grows, and required circuit functionalitybecomes available for placement in a higherabstractedmodular fashion.Figure 2. An automated design release process validates a printed circuit board design, which isstored (as revision) in a secure vault where its life cycle status can be managed.can see where it’s used in other design resources.The lifecycle status (prototype, production,etc) sets the reusable item’s approval state andhow it can be used, and it’s clear when a subitem(such as a constituent component) is nolonger approved.Enabled by the described vault technology,the capability to store, manage and recyclehigh-integrity design IP brings meaningful designreuse to electronics engineers with theright tools and systems. A unified electronicsdesign system with powerful data managementtools can connect directly to the managedvault system for easy design data access andmanagement, allowing verified, tracked designelements and sections of circuitry to bedropped into new designs at will. With all thesystems and tools in place, this then opens theopportunity to practise design for reuse (asopposed to design reuse) at a fundamentallevel. The difference here is that all elementsof design are captured and configured so thatthey can be easily re-used across any newfuture designs. From components (and theirconstituent models and data), to sheets ofschematic circuitry and up to fully releasedmodular designs, all are released into a vaultto essentially create a repository of manageddesign building blocks. And this is where theprocess discipline needs to be applied, basedon the commitment to a design for reuse approach.From the ground up, standardizednaming systems, data storage structures anddesign methodology need to be instigated (andrigorously applied) to bring order and integrityto the design process, which is based around acommon set of secure, lifecycle- managedvaults. The vaults become the essential sourcefor released design data IP, from the lowestUltimately, the concept of releasing design elementsto a fully managed vault provides a robustsystem for implementing a design forreuse methodology. And it goes way beyondsimply providing the mechanisms to accesspredefined design elements. By addressing thekey issues of managing data integrity and implementinga disciplined design methodologyand structure, the approach eliminates therisks associated with reusing even high level,multi-layered design sections.In practice it means that valuable design IPcan, and should, be reused with full confidencein its integrity. Implementing design reuseduring electronic product development is nolonger an act of blind faith or risky bravado –you can now know everything about the contentand viability of a reusable element, andmost importantly, know that its veracity is assured.And above all, implementing a designfor reuse methodology dictates a shift in thinkingand approach. Design reuse moves frombeing a desired bonus, or addition to electronicsdesign, to become the core of how you design,based around fully managed vaults. JTAG: low-cost boundary-scan suitecovers all applicationsJTAGLive Studio is a comprehensive package ofJTAG/boundary-scan tools that enable designersand manufacturing test engineers alike to developcomplete test and programming applications ata low price level. The benefits offered by theJTAG Technology for debugging, testing and insystemprogramming are not limited to complexdesigns with many JTAG devices. Designs withonly a few, even just one or two, JTAG devicescan also greatly benefit from this technologyduring all stages of the life cycle. A toolsetcapable of handling even the most (very) complexboundary-scan designs, however, often is noteconomically feasible for a company that onlyuses a few JTAG devices in its designs.News ID 16889Product News ADI: simulation tool eases developmentof RF systemsAnalog Devices released a new version of itspopular ADIsimRF design tool. The free designtool is the software accompaniment toADI’s complete portfolio of RF-to-digitalfunctional blocks, allowing engineers tomodel RF signal chains using devices fromacross ADI’s RF IC and data converter portfolio.ADIsimRF Version 1.7 adds a numberof new device models along with enhancedsupport for inter-stage mismatch calculations.The design tool provides calculationsfor the most important parameters withinan RF signal chain, including cascaded gain,noise figure, IP3, P1dB, and total powerconsumption.News ID 16894 PRQA: sophisticated and collaborativecode inspectionsPRQA announces a significant upgrade toQA•Verify quality management solution.QA•Verify already leverages the broad industryadoption of QA•C and QA•C++, providingteam-sharing collaboration, sophisticated codingstandards compliance, metrics and reportingfacilities across multiple software projects. Theadoption of structured code inspections remainssurprisingly low, despite the fact that the benefitsare well documented and compelling. Inspectionshave historically been a manual and intensiveeffort, difficult to scale as code volumeand complexity increases, along with the inevitableschedule and resourcing pressures on adevelopment team’s most experienced resources.News ID 16919April 201326
MICROCONTROLLERSSafer household appliances withlow-cost ARM Cortex-M based MCUsBy Vincent Onde, STMicroelectronicsHardware parity checkadoption in the embeddedmarket for general purposeMCUs, combined with anever-increasing number ofsystem monitoring and safetyfeatures, makes applicationssimpler to be certified, safetyrelateddevelopment taskseasier to be implemented,and most important, makeshousehold appliances safer. Since 2007, household appliance manufacturershave had to adhere to the IEC60335safety standard for all new designs. This standardcovers everything from mechanical systemsto embedded electronics to ensure theequipment is safe and reliable, and more specifically,that a failure will not present a safetyhazard to the user.The electronics section refers to another standard,the IEC60730, which covers automaticelectronic control for a wide range of applications.In particular, Annex H is important forembedded systems developers since it focuseson programmable devices. Microcontrollers arecommon in white goods, often used in multiples:typically, one manages the dashboard while anotherone handles valve and motor control.The standard distinguishes three software classes,A, B and C, depending on the danger apiece of equipment presents if it fails. If thesafety of the appliance does not rely on software,it falls into Class A - room thermostats orlighting controls, for example. At the oppositeend of the spectrum, if the software is intendedto prevent special hazards such as an explosionin electronically-fired gas burners, it is evaluatedas Class C. Class C is not covered in thisarticle since most household appliances whoseelectronic controls must prevent unsafe operationbelong to Class B. Class B includes washingmachines for example, with the potentialissues related to electronically controlled doorlocks or to thermal cut-offs of motors. TheIEC60730 table H.11.12.7 in Annex H lists themicrocontroller components to be tested, thefaults to be detected, and the acceptable measures,for both software class B and C. It includesthe CPU (registers and program counter), interrupts(handling and execution), clock frequencymonitoring, checks on variable memory(RAM) and invariable memory (flash, EEP-ROM), external communications, and peripherals.These checks are first done exhaustivelyduring the MCU boot, even before the systemstart-up code execution takes place. Why? Themain reason is that the RAM test is ‘destructive’and would corrupt the initialized variables.What is asked for within a RAM check? ForClass B, the standard requires single-bit DCfault detection (for instance stuck-at or couplingfault) to be done periodically. Since mostof the entry-level MCUs do not have paritybits included in their SRAM, the test must beimplemented by software. March algorithmsdetect these faults with a limited number ofpasses: March C- fits perfectly (using 10.n operations,n being the number of locations tobe tested) but March X (6.n operations) isalso accepted by test institutes in particularcases. Once the test is complete, the RAMmemory is erased (thus the term ‘destructivetest’). Carrying out a March test following thereset does not present particular difficulties. Ithas no real drawback other than slowing downthe start-up procedure a little bit: given thesmall quantity of embedded SRAM, usuallythis is not even noticeable. On the other hand,it can be quite a challenge if repeated duringrun-time.Firstly, it must be made transparent: the applicationmust handle the RAM without particularprotocol, as if the test were not implemented.Practically speaking, this imposes the followingconditions. It must be implemented in an interruptservice routine (ISR), served with the highestpriority. This guarantees the data will not beaccessed by the application while testing is done.A memory buffer must be provisioned, so thatthe content of the RAM area being checked canfirst be backed up and finally restored before resumingthe applicative tasks. Obviously, thisbuffer must also be periodically verified.Secondly, it must not suspend the applicationfor too much time. The check is usually splitin a number of partial tests to limit the timespent in this top level task. Still, the numberof locations tested at once cannot be lowerthan 3 consecutive locations (this is mandatoryto have coupling fault coverage), which representsno less than 30 successive read/write accessesusing a March C- algorithm. Although27 April 2013