6. Minimizing Delay

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Multistage Logic Networks10g 1= 1h 1= x/10xg 2= 5/3h 2= y/xyg 3= 4/3h 3= z/yzg 4= 1h 4= 20/z20Note:Capacitance unit= size of unitTransistor4∏i=1Problem: min f 1,.. f 4D=∑4D=∑i=1f i p i41D if i=G H =1∗ 5 3 ∗4 3 ∗1∗20 10 = 409f opt= f 1=...= f 4= 40 9 1/ 4=1.451 x10 = 5 3yx = 4 3zy =1 20 z =1.45z=13.8 y=12.7 x=14.6
Transistor sizing within the gatez=13.8 y=12.7 x=14.6z pmos= 2 3 ∗13.8=9.2 ;z nmos =1 3 ∗13.8=4.6y pmos= 2 4 ∗12.7=<strong>6.</strong>35=y nmosx pmos= 4 5 ∗14.6=11.7 ; x nmos = 1 5 ∗14.6=2.9
Page 1 and 2: Minimizing Delay
Page 4 and 5: INV X1Cin 3.6fF 4.2fFNAND2 X1Intrin
Page 6 and 7: Impact of velocity saturationI dsat
Page 8 and 9: Sizing to minimize delayNote:10g 1=
Page 12 and 13: Treat a path as a large compound ga
Page 14 and 15: Paths that Branch515901590D 1 = 151
Page 16 and 17: Finding the gate sizes for the opti
Page 18 and 19: Example: 3-stage pathxxy45A8xyB45Lo
Page 21 and 22: Best Number of Stages How many stag
Page 23 and 24: Sensitivity Analysis How sensitive
Page 25 and 26: Decoder with 4-input NANDA[3] A[3]
Page 27 and 28: Gate Sizes & DelayLogical Effort: G
Page 29 and 30: Method of Logical Effort•Compute
Page 31: Limits of Logical Effort Simplistic

6. Minimizing Delay

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