6. Minimizing Delay

12.07.2015 • Views

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6. Minimizing Delay

6. Minimizing Delay

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Logical Effort DefinitionLogical Effort: Ratio of logic gate’s input capacitance tothat of a inverter sized to have the samedrive strength.

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Logical Effort DefinitionLogical Effort: Ratio of logic gate’s input capacitance tothat of a inverter sized to have the samedrive strength.

Page 1: Minimizing Delay
Page 5 and 6: Logical Effort from previous tablet
Page 7 and 8: Sizing to minimize delay10g 1= 1h 1
Page 9 and 10: Multistage Logic Networks10g 1= 1h
Page 11 and 12: Transistor sizing within the gatez=
Page 13 and 14: Branching Effort Introduce branchin
Page 15 and 16: Optimum stage effortNmin D=∑ f i
Page 17 and 18: ExampleFind x and y to minimize del
Page 19: Example: 3-stage path Work backward
Page 22 and 23: Optimum Stage effort with freedom t
Page 24 and 25: Example: DecoderA[3:0] A[3:0]32 bit
Page 26 and 27: Gate Sizes & DelayLogical Effort: G
Page 28 and 29: Comparison of different gate choice
Page 30 and 31: Summary Logical effort is useful fo