6. Minimizing Delay

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Comparison of different gate choices for same decoder Compare many alternatives with a spreadsheet (or writea script)DesignNGPDNAND4-INV22529.8NAND2-NOR2220/9430.1INV-NAND4-INV32622.1NAND4-INV-INV-INV42721.1NAND2-NOR2-INV-INV420/9620.5NAND2-INV-NAND2-INV416/9619.7INV-NAND2-INV-NAND2-INV516/9720.4NAND2-INV-NAND2-INV-INV-INV616/9821.6
Method of Logical Effort•Compute path effort F=GBH•Estimate best number of stagesif number of stages in path is less than of equal toabove, add inverters (even numbers). N' is new pathlength•Determine best stage effort••Work backwards from output to•input to find the gate sizesNf opt=F=1N 'log 4F•
Page 1 and 2: Minimizing Delay
Page 4 and 5: INV X1Cin 3.6fF 4.2fFNAND2 X1Intrin
Page 6 and 7: Impact of velocity saturationI dsat
Page 8 and 9: Sizing to minimize delayNote:10g 1=
Page 10 and 11: Multistage Logic Networks10g 1= 1h
Page 12 and 13: Treat a path as a large compound ga
Page 14 and 15: Paths that Branch515901590D 1 = 151
Page 16 and 17: Finding the gate sizes for the opti
Page 18 and 19: Example: 3-stage pathxxy45A8xyB45Lo
Page 21 and 22: Best Number of Stages How many stag
Page 23 and 24: Sensitivity Analysis How sensitive
Page 25 and 26: Decoder with 4-input NANDA[3] A[3]
Page 27: Gate Sizes & DelayLogical Effort: G
Page 31: Limits of Logical Effort Simplistic

6. Minimizing Delay

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