6. Minimizing Delay

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Gate Sizes & DelayLogical Effort: G =Path Effort: F =Stage Effort:Path Delay:ˆf =D =Gate sizes: z = y =A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]10 10 10 10 10 10 10 10yzword[0]96 units of wordline capacitanceyzword[15]
Gate Sizes & DelayLogical Effort: G = 1 * 6/3 * 1 = 2Path Effort: F = GBH = 154Stage Effort:Path Delay:ˆ 1/3= F = 5.36fD= 3 fˆ+ 1+ 4 + 1 = 22.1Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]10 10 10 10 10 10 10 10yzword[0]96 units of wordline capacitanceyzword[15]
Page 1 and 2: Minimizing Delay
Page 4 and 5: INV X1Cin 3.6fF 4.2fFNAND2 X1Intrin
Page 6 and 7: Impact of velocity saturationI dsat
Page 8 and 9: Sizing to minimize delayNote:10g 1=
Page 10 and 11: Multistage Logic Networks10g 1= 1h
Page 12 and 13: Treat a path as a large compound ga
Page 14 and 15: Paths that Branch515901590D 1 = 151
Page 16 and 17: Finding the gate sizes for the opti
Page 18 and 19: Example: 3-stage pathxxy45A8xyB45Lo
Page 21 and 22: Best Number of Stages How many stag
Page 23 and 24: Sensitivity Analysis How sensitive
Page 25: Decoder with 4-input NANDA[3] A[3]
Page 29 and 30: Method of Logical Effort•Compute
Page 31: Limits of Logical Effort Simplistic

6. Minimizing Delay

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