Annual report 2008 - Europractice-IC

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ments:>Start new batch of wafersPhase PackagingIV: Qualification of of the ASICWhen customers customers only only need need prototypesof prototypes theirDevelopmentASIC, of qualification their ASIC, of qualificationqualification is not needed. procedureis not needed.Qualification requirements:However when prototypes are workingcorrectly However Qualification and when the prototypes customer hardware would areMedicallike to Qualification requirements:have working volumedevelopmentcorrectly production and the it customerto would think about like to the have “product vol-qualifi-Industrialis the rightMedicaltimeSpace Industrial >cation”. ume Qualification production it software is the rightConsumer Spacetime to think development about the “productqualification”. offers within their test so-ConsumerEuropracticelution Datalog, service a histograms, full qualification through Europractice offers within their test solutionone of theCPK,testCPhouse partners. service The a full qualification through one of thequalification procedure can range from test house partners. The qualification proceduretill can Space range qualification from Consumer, according Industry to the Mil-andConsumer, Industry and MedicalMedical itary, till Space JEDEC qualification standards... according to theMilitary, The JEDEC qualification standards... procedure will be discussedbetween procedure Europractice, will be discussed cus-The qualificationbetween tomer Europractice, and test house customer and and a full test qualificationfull qualification flow will be flow prepared. will be To prepared. speedhouseand aTo speed up up the the procedure, most of of the testsare running are running parallel. in parallel. Special Special burn-in burn-in boardswill be boards developed will for be reliability developed tests. for reliabilitytests.By courtesy of MASER Engineering>Phase V: Volume production & test activitiesPhase V: Volume production & test activitiesOnce the ASIC has beenWafer production qualified, the ASIC isOnce the ASIC has been qualified, the ready ASIC for is volume ready for production.will During be monitored. the ramp-up Once the ASIC runs intovolume production. Duringthe ramp-up phase, yield and processProbe testhigher volume, the test solution can be phase, transferred yield and to test process houses in the Far East. Inthat case the test boards are copied, will the original be monitored. test board Once will remain in our Europeantest houses so that yield and process the ASIC monitoring runs into is higherPackagingstill possible.volume, the test solutioncan be transferredFinal testto test houses in the FarEast. In that case thetest boards are copied,Yield & processthe original test boardmonitoringwill remain in our Europeantest houses so thatDelivery testedyield and process monitoringis stillcomponentsBy courtesy of Microtestpossible.Start new batch of wafersStart new batch of wafersPackagingPackagingDevelopment ofqualification procedureDevelopment ofqualification procedureQualification hardwareQualification development hardwaredevelopmentQualification softwareQualification softwaredevelopmentdevelopmentDatalog, Datalog, histograms, histograms,CPK, CPK, CPWafer productionWafer productionProbe testPackaging Probe testFinal testPackagingYield & processmonitoringFinal testDelivery testedcomponents Yield & processmonitoring6 europractice | a total solutionDelivery testedcomponents
EUROPRACTICEoffers deep submicron design support serviceSynthesis and layout of deep submicron chips is notstraightforward. You need a highly trained team of engineersequipped with expensive state-of-the art softwaretools. The chips are growing in size whereas thetechnology dimensions are getting smaller. Because ofthis, designers have to to understand how how to tackle to tackle issues issuesclock-skew, like: clock-skew, latencies latencies of interacting of interacting clock clock domains, do-like:IR-drop mains, IR-drop on the on power the power distribution, distribution, electro-migration electro-migrationsignal and integrity signal integrity issues, handling issues, handling up to 8 layers up to of 8andmetal layers in of metal the back-end, in the back-end, incorporating incorporating IP blocks IP blocks in thedesign, in the design, on-chip on-chip variation, variation, design design for packaging, for packaging, etc.etc.Supporting high-level designers, EUROPRACTICE ICService Supporting provides high-level a design designers, support EUROPRACTICE service starting IC from Servicecode provides or synthesized a design support netlist. service The service starting includes fromRTLthe RTL whole code or back-end synthesized design netlist. flow: The virtual service prototyping, includesphysical the whole synthesis, back-end deep-submicron design flow: virtual layout, prototyping, timing analysis,physical simulation, synthesis, ATPG, deep-submicron tape-out preparation, layout, etc. timinganalysis, simulation, ATPG, tape-out preparation, etc.The service is equipped with state-of-the art tools fromthe The major service vendors: is equipped the Synopsys with state-of-the Galaxy art and tools Cadence fromEncounter the major Platforms. vendors: the Synopsys Galaxy and CadenceEncounter Platforms.In the past many circuits were taped out successfullyIn the both past for many in-house circuits developed were taped Systems-On-a-Chipout successfullyas both for for ASICs in-house developed developed by third Systems-On-a-Chip party design houses, as forresearch ASICs developed institutes by and third universities. party design Many of houses, these circuitsearchincluded institutes IP blocks and universities. like analog Many full custom of these blocks, cir-re-memory cuits included macro’s IP (even blocks from like analog different full vendors), custom blocks, specialI/O memory and RTL macro’s level (even (soft or from firm) different IP. vendors), specialI/O and RTL level (soft or firm) IP.Procedures are in place to offer standard and staggeredProcedures I/O configurations are in place and to configurations offer standard with and bondingeredpads I/O equally configurations spread over and configurations the standard-cell with core, bond-forstag-flip-chip ing pads application. equally spread over the standard-cell core, forflip-chip application.Some circuit complexities handled are: up to 71 milliontransistors, Some circuit several complexities hundred handled interrelated are: up to gated 71 million clockdomains transistors, and several technologies hundred from interrelated many different gated vendors clockdown domains to 90nm. and technologies from many different vendorsdown to 90nm.IMEC’s flexible-air-interface baseband plaform (TSMC 90nm CMOS)Layout of a 40 million transistor circuit featuring RAMS and other(By courtesy of IMEC)IP in Chartered Semiconductor 0.13µ CMOS – 46.5 mm 2(By courtesy of IMEC)A mixed signal control ASIC designed in IMEC’s radiation-hardened-by-DesignLayout of a 3.7 DARE180 million-transistor (UMC 0.18) circuit library featuring for the digital several part memory plusanalog blocks blocks and PLL using UMC layout-based 0.18µ CMOS radiation (6 metal countermeasures.layers) – 20 mm 2(By courtesy of of IMEC)europractice | a total solution7
Page 4 and 5: Table of contentsForeword .........
Page 6 and 7: Phase I: ASIC DesignWhen When custo
Page 10: Low cost IC prototypingThe The cost
Page 13 and 14: WEB sitehttp://www.europractice-ic.
Page 15 and 16: 0.18µ 29%0.25µ 15%MPW designs in
Page 17 and 18: AustraliaAustriaBelarusBelgiumBrazi
Page 19 and 20: A Low-Power and Accurate CMOS Tempe
Page 21 and 22: A Neural Implant ASIC for the Resto
Page 23 and 24: A Sub-μW Fully Tunable CMOS DPS fo
Page 25 and 26: the power supply mechanism. A remot
Page 27 and 28: X-band Monolithic RadiometerUnivers
Page 29 and 30: A 64 PixelModulated Light CameraEle
Page 31 and 32: Universal chipset for Ultra-Wideban
Page 33 and 34: figure 2: Results obtained from cal
Page 35 and 36: List of Customers per country and n
Page 37 and 38: CUSTOMER TOWN Numberof ASICsOptek S
Page 39 and 40: CUSTOMER TOWN Numberof ASICsPortuga
Page 41 and 42: CUSTOMER TOWN Numberof ASICsLinear
Page 44: All information for MPW runs schedu

Annual report 2008 - Europractice-IC

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