MCP3421 - Microchip

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MCP34215.4 General CallThe device acknowledges the general call address(0x00 in the first byte). The meaning of the general calladdress is always specified in the second byte. Referto Figure 5-5. The device supports the following twogeneral calls.For more information on the general call, or other I 2 Cmodes, please refer to the Phillips I 2 C specification.5.4.1 GENERAL CALL RESETThe general call reset occurs if the second byte is‘00000110’ (06h). At the acknowledgement of thisbyte, the device will abort current conversion andperform an internal reset similar to a Power-On-Reset(POR). All configuration and data register bits are resetto default values.5.4.2 GENERAL CALL CONVERSIONThe general call conversion occurs if the second byteis ‘00001000’ (08h). All devices on the bus initiate aconversion simultaneously. When the device receivesthis command, the configuration will be set to the One-Shot Conversion mode and a single conversion will beperformed. The PGA and data rate settings areunchanged with this general call.STARTLSB STOP5.5 High-Speed (HS) ModeThe I 2 C specification requires that a high-speed modedevice must be ‘activated’ to operate in high-speedmode. This is done by sending a special address byteof “00001XXX” following the START bit. The “XXX” bitsare unique to the High-Speed (HS) mode Master. Thisbyte is referred to as the High-Speed (HS) MasterMode Code (HSMMC). The MCP3421 device does notacknowledge this byte. However, upon receiving thiscode, the device switches on its HS mode filters andcommunicates up to 3.4 MHz on SDA and SCL buslines. The device will switch out of the HS mode on thenext STOP condition.For more information on the HS mode, or other I 2 Cmodes, please refer to the Phillips I 2 C specification.5.6 I 2 C Bus CharacteristicsThe I 2 C specification defines the following busprotocol:• Data transfer may be initiated only when the busis not busy• During data transfer, the data line must remainstable whenever the clock line is HIGH. Changesin the data line while the clock line is HIGH will beinterpreted as a START or STOP conditionAccordingly, the following bus conditions have beendefined using Figure 5-6.S0 0 0 0 0 0 0 0 A X X X X X X X X AS5.6.1 BUS NOT BUSY (A)Both data and clock lines remain HIGH.First Byte ACK(General Call Address)Note:FIGURE 5-5:Format.Second ByteGeneral Call AddressACKThe I 2 C specification does not allow“00000000” (00h) in the second byte.5.6.2 START DATA TRANSFER (B)A HIGH to LOW transition of the SDA line while theclock (SCL) is HIGH determines a START condition. Allcommands must be preceded by a START condition.5.6.3 STOP DATA TRANSFER (C)A LOW to HIGH transition of the SDA line while theclock (SCL) is HIGH determines a STOP condition. Alloperations can be ended with a STOP condition.5.6.4 DATA VALID (D)The state of the data line represents valid data when,after a START condition, the data line is stable for theduration of the HIGH period of the clock signal.The data on the line must be changed during the LOWperiod of the clock signal. There is one clock pulse perbit of data.Each data transfer is initiated with a START conditionand terminated with a STOP condition.DS22003E-page 22© 2009 Microchip Technology Inc.
MCP34215.6.5 ACKNOWLEDGE AND NON-ACKNOWLEDGEThe Master (microcontroller) and the slave (MCP3421)use an acknowledge pulse as a hand shake of communicationfor each byte. The ninth clock pulse of eachbyte is used for the acknowledgement. The clock pulseis always provided by the Master (microcontroller) andthe acknowledgement is issued by the receiving deviceof the byte (Note: The transmitting device must releasethe SDA line during the acknowledge pulse.). Theacknowledgement is achieved by pulling-down theSDA line “LOW” during the 9th clock pulse by thereceiving device.During reads, the Master (microcontroller) canterminate the current read operation by not providingan acknowledge bit (not Acknowledge (NAK)) on thelast byte. In this case, the MCP3421 device releasesthe SDA line to allow the Master (microcontroller) togenerate a STOP or repeated START condition.The non-acknowledgement (NAK) is issued byproviding the SDA line to “HIGH” during the 9th clockpulse.SCL(A) (B) (D) (D) (C) (A)SDASTARTCONDITIONADDRESS OR DATAACKNOWLEDGE ALLOWEDVALID TO CHANGESTOPCONDITIONFIGURE 5-6:Data Transfer Sequence on I 2 C Serial Bus.© 2009 Microchip Technology Inc. DS22003E-page 23
Page 1 and 2: MCP342118-Bit Analog-to-Digital Con
Page 3 and 4: MCP34211.0 ELECTRICALCHARACTERISTIC
Page 5 and 6: MCP3421TEMPERATURE SPECIFICATIONSEl
Page 7 and 8: MCP34212.0 TYPICAL PERFORMANCE CURV
Page 10 and 11: MCP34213.4 Serial Data Pin (SDA)SDA
Page 12 and 13: MCP34214.5 Input Voltage RangeThe d
Page 14 and 15: MCP34214.9.2 CONVERTING THE DEVICEO
Page 16 and 17: MCP34215.2 Configuration RegisterTh
Page 18 and 19: MCP3421Start bitAddressAddress Byte
Page 20 and 21: MCP34211 9 1 9 1 9 1 9 19SCLSDA1 1
Page 24 and 25: MCP3421TABLE 5-4:I 2 C SERIAL TIMIN
Page 26 and 27: MCP3421T FT HIGHSCLSDAT SPT SU:STAT
Page 28 and 29: MCP34216.1.3 DEVICE COMMUNICATION T
Page 30 and 31: MCP34216.2.3 PRESSURE MEASUREMENTFi
Page 32 and 33: MCP3421NOTES:DS22003E-page 32© 200
Page 34 and 35: MCP3421FIGURE 7-3:Example of PICkit
Page 36 and 37: MCP3421bN4E1EPIN1IDBYLASER MARK1 2
Page 42: WORLDWIDE SALES AND SERVICEAMERICAS

MCP3421 - Microchip

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