<strong>SH564128FH8N0QHSCR</strong>April 11, 2011• April 11, 2011Corrected part number to <strong>SH564128FH8N0QHSCR</strong>.• January 25, 2011Datasheet released.Revision HistoryCorporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.comEurope: 5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757Asia/Pacific: Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-39929032
<strong>SH564128FH8N0QHSCR</strong>April 11, 20114GByte (512Mx64) DDR3 SDRAM Module - 256Mx8 Based240-pin DIMM, Unbuffered, Non-ECCFeatures• Standard = JEDEC• Configuration = Non-ECC• Number of Module Ranks = 2• Number of Devices = 16• V DD = V DDQ = 1.5V• V DDSPD = 1.7V to 3.6V• Cycle Time = 1.5ns• CAS Latency = 6, 7, 8, 9• Additive Latency = 0, CL-1, and CL-2• CAS Write Latency (CWL) = 5, 6, 7• Burst Length = BC4, BL8, BC4 or BL8 (on the fly)• Burst Length = Nibble Sequential & Interleave Mode• Internal Banks per SDRAM = 8• Refresh = 8K/64ms• Device Package = FBGA• Lead Finish = Gold• Length x Height = 133.35mm x 30.00mm• No. of sides = Double-sided• Mating Connector (Examples)Vertical = AMP - 5-1932000-9• ZQ calibration supported• On chip DLL align DQ, DQS and DQS transitionwith CK transition• DM write data-in at both the rising and fallingedges of the data strobe• All addresses and control inputs latched on therising edges of the clock• Dynamic On Die Termination supported• Driver strength selected by EMRS• Asynchronous RESET pin supported• Write Levelization supported• 8-bit pre-fetchAddressingDevice Configuration256Mx8Number of Internal Banks 8Bank AddressBA0 - BA2Auto prechargeA10/APBC switch on the flyA12/BCRow AddressA0 - A14Column AddressA0 - A9Pin Description TableSymbol Type Polarity FunctionCK0~CK1,CK0~CK1SSTL_15DifferentialCrossingCK and CK are differential clock inputs. All the DDR3 SDRAM address/control inputs are sampledon the crossing of the positive edge of CK and the negative edge of CK. Output (read) datais referenced to the crossing of CK and CK (Both directions of crossing).CKE0, CKE1 SSTL_15 Active HighCS0, CS1 SSTL_15 Active LowODT0, ODT1 SSTL_15 Active HighActivates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivatingthe clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.Enables the associated SDRAM command decoder when low and disables the commanddecoder when high. When decoder is disabled, new commands are ignored but previous operationscontinue.This signal provides for external rank selection on systems with multiple ranks.When high, termination resistance is enabled for all DQ, DQS, DQS and DM pins, assumingthis function is enabled on the DRAM.BA0~BA2 SSTL_15 - Selects which SDRAM bank of the eight is activated.Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.comEurope: 5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757Asia/Pacific: Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-39929033
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