SH564128FH8N0QHSCR - Itautec

SH564128FH8N0QHSCRApril 11, 2011Speed Bin Tables Notes1. The CL setting and CWL setting result in t CK(AVG) min and t CK(AVG) max requirements. When making a selectionof t CK(AVG) , both need to be fulfilled: Requirements from CL setting as well as requirements from CWLsetting.2. t CK(AVG) min limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by theDLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smallerJEDEC standard t CK(AVG) value (2.5, 1.875, or 1.5) when calculating CL [nCK] = t AA [ns] / t CK(AVG) [ns],rounding up to the next ‘Supported CL’.3. t CK(AVG) max limits: Calculate t CK(AVG) = t AA max / CL SELECTED and round the resulting t CK(AVG) down tothe next valid speed bin (i.e. 3.3ns, 2.5ns, or 1.875 ns). This result is t CK(AVG) max corresponding to CLSELECTED.4. ‘Reserved’ settings are not allowed. User must program a different value.5. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table whichare not subject to Production Tests but verified by Design/Characterization.Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.comEurope: 5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757Asia/Pacific: Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-399290334