MC95FR464_DS_REV2.0_20120104.pdf - ABOV Semiconductor
MC95FR464_DS_REV2.0_20120104.pdf - ABOV Semiconductor
MC95FR464_DS_REV2.0_20120104.pdf - ABOV Semiconductor
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MC95FR332/432/364/464t LAG/SS(OUTPUT)t LEADt XCKXCK(UCPOL=0)(OUTPUT)0.8VDD0.2VDDt XCKLt XCKHXCK(UCPOL=1)(OUTPUT)t SIMt HIMMISO(INPUT)MSBBIT 6 … 1LSBt SOMt HOMt DISMOSI(OUTPUT)MSBBIT 6 … 1LSBFigure 7.4 SPI slave mode timing (UCPHA = 0, MSB first)t LAG/SS(INPUT)t LEADt XCKXCK(UCPOL=0)(INPUT)0.8VDD0.2VDDt XCKLt XCKHXCK(UCPOL=1)(INPUT)t SOS t HOS t DISMISO(OUTPUT)MSBBIT 6 … 1LSBt SIMt HIMMOSI(INPUT)MSBBIT 6 … 1LSBFigure 7.5 SPI / Synchronous slave mode timing (UCPHA = 1, MSB first)NOTE When in Synchronous mode, the START bit becomes MSB and the 1 st or 2 nd STOP bit becomes LSB.28 January, 2012 Rev.2.0
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