MC95FR464_DS_REV2.0_20120104.pdf - ABOV Semiconductor

MC95FR332/432/364/46410.2 External InterruptThe External Interrupts are triggered by the INT0, INT1, INT2, INT3 pins. The External Interrupts canbe triggered by a falling or rising edge or a low or high level. The trigger mode and trigger level iscontrolled by External Interrupt Edge Register (EIEDGE) and External Interrupt Polarity Register(EIPOLA). When the external interrupt is enabled and is configured as level triggered, the interrupt willtrigger as long as the pin is held low or high. External interrupts are detected asynchronously. Thisimplies that these interrupts can be used for wake-up sources from stop mode. The interrupt requestsfrom INT0, INT1, INT2, INT3 pins can be monitored through the External Interrupt Flag Register(EIFLAG).INT0 Pin(P36)2EIFLAG0INT0 InterruptINT1 Pin(P37)2EIFLAG1INT1 InterruptINT2 Pin(P21)2EIFLAG2INT2 InterruptINT3 Pin(P22)2EIFLAG3INT3 InterruptEIEDGE, EIPOLA[AD H] EIEDGE[AE H] EIPOLAFigure 10.1 External Interrupt trigger condition50 January, 2012 Rev.2.0