MC95FR464_DS_REV2.0_20120104.pdf - ABOV Semiconductor

MC95FR332/432/364/4649. I/O PORTS9.1 IntroductionThe MC95FR332/432/364/464 has six I/O ports (P0, P1, P2, P3, P4, P5). Each port can be easilyconfigured by software whether to use internal pull up resistor or not, whether to use open drainoutput or not, or whether the pin is input or output. Also P0 includes function that can generateinterrupt when the state of P0 changes.9.2 Register Description9.2.1 Data Register (Px)Data Register is a bidirectional I/O port. If ports are configured as output ports, data can be written tothe corresponding bit in the Px. If ports are configured as input ports, the port value can be read fromthe corresponding bit in the Px.9.2.2 Direction Register (PxIO)The PxnIO bit in the PxIO register selects the direction of this pin. If PxnIO is written logic one, Pxn isconfigured as an output pin. If PxnIO is written logic zero, Pxn is configured as an input pin. All bitsare cleared by a system reset.9.2.3 Pull-up Resistor Selection Register (PxPU)All ports P0, P1, P2, P3, P4, P5 have optional internal pull-ups. The PxnPU bit in the PxPU registerallows the use of pull-up resistor. If PxnPU is written logic one, the pull-up resistor is activated. IfPxnPU is written logic zero, the pull-up resistor is deactivated. When the port is configured as an inputport, internal pull-up is deactivated regardless of the PxnPU bit. After reset, all pull-up resistors areswitched off except those of P3[5:2], P4[7:0], P5[3:0]. According to PKG types, some of these portsare omiited, so to maintain input status, the internal pull-ups for these ports are activated.9.2.4 Open-drain Selection Register (PxOD)The PxnOD bit in the PxOD register controls the port type when configured as an output port. IfPxnOD is written logic one, the port becomes open-drain type. If PxnOD is written logic zero, the portbecomes push-pull type. After reset, open-drain function is disabled.Caution : Port 0 has no open drain control register.9.2.5 Pull-up Control Register (PxBPC)When the external VDD drops below the BODOUT0 level, the ports can be selectively configured asinput ports with pull-up resistors activated regardless of the PxnIO. In this case, the port direction ischanged by hardware automatically. If PxnBPC is written logic one, this function is enabled. IfPxnBPC is written logic zero, the port maintain its status even if the device enters stop mode after theexternal VDD is fallen below the BODOUT0 level. After reset, PxnBPC is set to 1 allowing automaticport direction change due to voltage drop.40 January, 2012 Rev.2.0