LMX9830 Bluetooth™ Serial Port Module

8.0 Functional Description8.1 BASEBAND AND LINK MANAGEMENTPROCESSORSBaseband and Lower Link control functions are implementedusing a combination of National Semiconductor’sCompactRISC 16-bit processor and the Bluetooth LowerLink Controller. These processors operate from integratedROM memory and RAM and execute on-board firmwareimplementing all Bluetooth functions.8.1.1 Bluetooth Lower Link ControllerThe integrated Bluetooth Lower Link Controller (LLC) complieswith the Bluetooth Specification version 2.0 andimplements the following functions:■ Adaptive Frequency Hopping■ Interlaced Scanning■ Fast Connect■ Support for 1, 3, and 5 slot packet types■ 79 Channel hop frequency generation circuitry■ Fast frequency hopping at 1600 hops per second■ Power management control■ Access code correlation and slot timing recovery8.1.2 Bluetooth Upper Layer StackThe integrated upper layer stack is prequalified andincludes the following protocol layers:■ L2CAP■ RFComm■ SDP8.1.3 Profile supportThe on-chip application of the LMX9830 allows full standaloneoperation, without any Bluetooth protocol layer necessaryoutside the module. It supports the Generic AccessProfile (GAP), the Service Discovery Application Profile(SDAP), and the Serial Port Profile (SPP).The on-chip profiles can be used as interfaces to additionalprofiles executed on the host. The LMX9830 includes aconfigurable service database to answer requests with theprofiles supported.8.1.4 Application with command interfaceThe module supports automatic slave operation eliminatingthe need for an external control unit. The implementedtransparent option enables the chip to handle incomingdata raw, without the need for packaging in a special format.The device uses a pin to block unallowed connections.This pincode can be fixed or dynamically set.Acting as master, the application offers a simple but versatilecommand interface for standard Bluetooth operationlike inquiry, service discovery, or serial port connection.The firmware supports up to seven slaves. Default Link Policysettings and a specific master mode allow optimizedconfiguration for the application specific requirements. Seealso Section "Integrated Firmware" on page 30.8.1.5 MemoryThe LMX9830 introduces 16 kB of combined system andPatch RAM memory that can be used for data and/or codeupgrades of the ROM based firmware. Due to the flexiblestartup used for the LMX9830 operating parameters likethe Bluetooth Device Address (BD_ADDR) are defined duringboot time. This allows reading out the parameters of anexternal EEPROM or programming them directly overUART.8.1.6 External memory interfacesAs the LMX9830 is a ROM based device with no on-chipnon volatile storage, the operation parameters will be lostafter a power cycle or hardware reset. In order to prevent reinitializing such parameters, patches or even user data, theLMX9830 offers two interfaces to connect an externalEEPROM to the device:■ µ-wire/SPI■ Access.bus (I 2 C compatible)The selection of the interface is done during start up basedon the option pins. See Table 17 on page 17 for the optionpin descriptions.8.1.7 µ-wire/SPI interfaceIn case the firmware is configured by the option pins to usea µ-wire/SPI EEPROM, the LMX9830 will activate that interfaceand try to read out data from the EEPROM. The externalmemory needs to be compatible to the reference listedin Table 10 on page 13. The largest size EEPROM supportedis limited by the addressing format of the selected NVM.The device must have a page size equal to N x 32 bytes.The firmware requires that the EEPROM supports Pagewrite. Clock must be HIGH when idle.Table 10. M95640-S EEPROM 8Kx8ParameterValueSupplier ST MicroelectronicsSupply Voltage 1 1.8 - 3.6VSPI compatible (positive clock SPIInterface Modes)Memory Size 8K x 8, 64kbitClock Rate 1 2 MHzAccessByte and Page Write (up to32bytes)1. Parameter range reduced to requirements of Nationalreference designLMX983013 www.national.com