Marvell ARMADA 16x Applications Processor Family

Marvell ® ARMADA 16x Applications Processor Family Hardware Manual
Table 7:
Voltage, Temperature, and Frequency Electrical Specifications (Continued)
Symbol Description Min Typical Max Units Notes
NOTE:
1. Minimum/maximum junction temperature depends on SKU
2. The case temperature spec for Marvell ® ARMADA 16x Applications Processor Family is a function of the Ψjt value
that varies pending OEM system configuration. Ψjt value should be modeled and/or tested for each system
configuration.
3. Allowable case temperature should be calculated using following formula. Maximum Ψjt can be used for maximum
allowable case temperature calculation where testing or modeling resources are nor available or system can absorb the
extra guard band introduced using max Ψjt values
4. Tcase (max) = Tj (max) - Ψjt * P (max)
5. Tcase (max) = Maximum allowable case temperature (°C).
6. Tj (max) = Maximum allowable junction temperature (°C)
7. P (max) = Maximum Sustainable ARMADA Power (W)
8. System design must ensure that the device case temperature is maintained within the specified limits. In some system
applications it may be necessary to use external thermal management (for example, a package-mounted heat
spreader) or configure the device to limit power consumption and maintain acceptable case temperatures.
9. The voltage ranges specified for VDD_CORE are the targeted voltage ranges for the product. These ranges may
extend or narrow depending on actual product performance and product SKUs. Marvell recommends that extended
voltage and current capabilities be designed into the power management IC to accommodate future changes to this
specification without requiring changes to the power management IC.
10. Maximum allowable operating voltage on VDD_CORE.
11. Maximum allowable voltage on VDD_CORE to meet maximum 1.4 W Pmax
12. Mode 0 is PCLK = 156 MHz and DCLK = 156 MHz
13. Mode 1 is PCLK = 400 MHz and DCLK = 200 MHz
14. Mode 2 is PCLK = 624 MHz and DCLK = 312 MHz
15. Mode 2.3 is PCLK = 624 MHz and DCLK = 156 MHz
16. Mode 3 is PCLK = 800 MHz and DCLK = 400 MHz
17. Mode 3.1 is PCLK = 800 MHz and DCLK = 200 MHz
18. Mode 4 is PCLK = 1.066 GHz and DCLK = 533 MHz
19. Mode 4.1 is PCLK = 1.066 GHz and DCLK = 355 MHz
20. Maximum VDD_CORE power (Pmax) is 1.5W
21. Maximum full chip power (Pmax_fullchip) is 2.0W
22. Maximum full chip power (Pmax_fullchip) is 1.9W.
Doc. No. MV-S301545-00 Rev. - Copyright © 2010 Marvell
Page 32
November 2010 PUBLIC RELEASE