Marvell ARMADA 16x Applications Processor Family

Marvell ® ARMADA 16x Applications Processor Family Hardware Manual
7.1.1 Measurement Conditions
Table 13:
The diagrams in the section use the following conventions:
Standard Input, Output, and I/O-Pin AC Operating Conditions
Symbol Description Min Typical Max Units
C IO IO capacitance, all standard I/O pins — — 5 pf
Figure 8:
SDRAM_CLKn
SDRAM_CLK
Table 14:
Differential Clock
Clock Parameters
V ID v x
Clock Crossing
Symbol Description Min Typical Max Units
Vx Differential Clock Cross over point relative to gnd 0.45*VDDQ — 0.55*VDDQ V
VID DC Differential Output Voltage 1.36 1.44 1.52 V
7.1.2 DDR SDRAM Timing Diagrams and Specifications
Figure 9 through Figure 12 shows the typical LPDDR1 SDRAM timings. Figure 15 shows the skew
timings. Refer to Table 15 for the DDR specifications. Refer to the JEDEC Spec for complete timing
diagrams and specifications.
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Doc. No. MV-S301545-00 Rev. -
Page 42
Copyright © 2010 Marvell
November 2010 PUBLIC RELEASE