Marvell ARMADA 16x Applications Processor Family

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Marvell ® ARMADA 16x Applications Processor Family Hardware Manual Table 15: t FAW t XSR t CKE Maximum number of ACTIVE or per-bank refreshes within this period. Self refresh exit to next valid command delay CKE minimum pulse width (High and low pulse width) 2 SDRAM_TIMING_5[tFAW] 2 DCLK 1 SDRAM_TIMING_3[tXSNR] SDRAM_TIMING_3[tXSRD] 511 DCLK 1 SDRAM_TIMING_4[tCKE] 7 DCLK t MRD Mode Register Set command cycle time 1 SDRAM_TIMING_2[tMRD] 7 DCLK t REFI Auto-Refresh Interval Counter 1 SDRAM_TIMING_1[tREFI] 65535 FCLK t RFC Refresh to Active or Refresh to Refresh internal 1 SDRAM_TIMING_2[tRFC] 511 DCLK t CCD CAS# to CAS# command delay 1 SDRAM_TIMING_1[tCCD] 7 DCLK t RTP t INIT_COU NT t INIT_COU NT_NOP DDR Timing Specifications (Continued) Symbol Description Min Typical Max Units Internal Read to Precharge command delay Power up delay after stable power and clocks Power up delay after stable power and clocks 1 SDRAM_TIMING_1[tRTP] 7 DCLK 1 SDRAM_TIMING_4[INIT_COUNT] 255 DCLK 1 SDRAM_TIMING_4[INIT_COUNT _NOP] 255 DCLK NOTE: 1. Timing Specified to Reference Load (50 Ohms T line connected to 20pF) 2. The setup and hold timing is for reference slew rate of 1V/ns for DQ and 1V/ns for DQS. For slower slew rates, apply 100ps extra derating for setup/hold. 3. Drive Strength reference setting for timing ZPR=ZNR=0111 Table 16: DDR Timing Specifications for 533 MHz (VDD_M = 1.8V) Symbol Description Min Typical Max Units Notes t CK(Jitter) CLK Jitter at output pin (c-c) -100 — 100 ps t CL Clock low level width 0.47 — 0.53 t CK t CH Clock high level width 0.47 — 0.53 t CK t CK_DC Duty Cycle at output pin 0.42 — 0.53 t CK t DQTVB DQ Valid time before DQS 0.27 — — ns 1 t DQTVA DQ Valid time after DQS 0.3 — — ns 1 t ATVB ADDR/CMD/CNTRL (RAS, CS, CAS, WE, CKE, ADDR) Valid time before CK 0.6 — — ns 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Doc. No. MV-S301545-00 Rev. - Page 48 Copyright © 2010 Marvell November 2010 PUBLIC RELEASE
AC Electrical Characteristics DDR SDRAM Timing Diagrams and Specifications Table 16: t ATVA ADDR/CMD/CNTRL (RAS, CS, CAS, WE, CKE, ADDR) Valid time after CK 0.64 — — ns 1 t DQSSmc DQS Output access time from CLK pos edge — — 0.08 ns 1 t SUmc t HDmc Max Setup skew allowed between DQ and DQS during READ from DQS transition Hold factor for valid DQ w.r.t DQS rising/falling edge during READ — — 0.29 ns 2 0.65 — — ns 2 t DIPWmc DQ and DM output pulse width 0.45 — — t CK t DQSHmc DQS output high pulse width 0.45 — — t CK t DQSLmc DQS output low pulse width 0.45 — — t CK t DSSmc DQS falling edge to CLK-CLKn rising edge 0.4 — — t CK t DSHmc t DQSSmc DQS falling edge from CLK-CLKn rising edge Write command to first DQS latching transition 0.4 — — t CK -0.1 — 0.1 t CK t WPREmc DQS write preamble 0.4 — — t CK t WPSTmc DQS write postamble 0.45 — 0.55 t CK t IPWmc Address and Control output pulse width 0.9 — — t CK t RPREmc DQS read preamble 0.9 — 1.1 t CK t RPSTmc DQS read postamble 0.4 — 0.6 t CK t DQSCKmc DQS input access time from CLK/CLKn 2.0 — 7.0 ns t LZmc t HZmc DDR Timing Specifications for 533 MHz (VDD_M = 1.8V) (Continued) Symbol Description Min Typical Max Units Notes DQ and DQS low-impedance time from CLK/CLKn DQ and DQS high-impedance time from CLK/CLKn 1 — — ns — — 7 ns NOTE: 1. Timing Specified to Reference Load (50 Ohms T line connected to 20pF) 2. The setup & hold timing is for reference slew rate of 1V/ns for DQ and 1V/ns for DQS. For slower slew rates, apply 100ps extra derating for setup/hold. 3. Drive Strength reference setting for timing ZPR=ZNR=0111 Table 17: DDR Timing Specifications for 400 MHz (VDD_M = 1.8V) Symbol Description Min Typical Max Units Notes t CK(Jitter) CLK Jitter at output pin (c-c) -100 — 100 ps 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Copyright © 2010 Marvell Doc. No. MV-S301545-00 Rev. - November 2010 PUBLIC RELEASE Page 49
Page 1 and 2: Cover Marvell ® ARMADA 16x Applica
Page 3 and 4: Table of Contents Table of Contents
Page 5 and 6: Table of Contents 8.2 EPD Controlle
Page 7 and 8: List of Figures List of Figures Rev
Page 9 and 10: List of Tables List of Tables Revis
Page 11 and 12: Revision History Public Release, Re
Page 13 and 14: Introduction Product Summary 1 Intr
Page 15 and 16: Introduction Product Summary Table
Page 17 and 18: Introduction Number Representation
Page 19 and 20: Product Overview 2 Product Overview
Page 21 and 22: Pin and Ball Map Views ARMADA 168 (
Page 23 and 24: Pin and Ball Map Views ARMADA 162 (
Page 25 and 26: Package Information Introduction 4
Page 27 and 28: Package Information ARMADA 16x Appl
Page 29 and 30: Maximum Ratings and Operation Condi
Page 31 and 32: Maximum Ratings and Operation Condi
Page 33 and 34: Electrical Specifications DC Voltag
Page 35 and 36: Electrical Specifications DC Voltag
Page 37 and 38: Electrical Specifications Oscillato
Page 39 and 40: Electrical Specifications Oscillato
Page 41 and 42: AC Electrical Characteristics DDR S
Page 47: AC Electrical Characteristics DDR S
Page 53 and 54: AC Electrical Characteristics Stati
Page 65 and 66: AC Electrical Characteristics NAND
Page 67 and 68: AC Electrical Characteristics NAND
Page 69 and 70: AC Electrical Characteristics SD Ho
Page 71 and 72: AC Electrical Characteristics LCD C
Page 77 and 78: AC Electrical Characteristics SSP T
Page 79 and 80: AC Electrical Characteristics TWSI
Page 81 and 82: AC Electrical Characteristics TWSI
Page 83 and 84: AC Electrical Characteristics JTAG
Page 85 and 86: AC Electrical Characteristics USB 2
Page 87 and 88: AC Electrical Characteristics USB 2
Page 89 and 90: AC Electrical Characteristics PCI E
Page 91 and 92: AC Electrical Characteristics Ether
Page 93 and 94: AC Electrical Characteristics Power
Page 95 and 96: AC Electrical Characteristics Power
Page 97 and 98: Design Guidelines and Checklist DDR
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Design Guidelines and Checklist EPD
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Design Guidelines and Checklist Sch
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Design Guidelines and Checklist Sch
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Back Cover Marvell Semiconductor, I
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Marvell ARMADA 16x Applications Processor Family

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