Marvell ARMADA 16x Applications Processor Family

Marvell ® ARMADA 16x Applications Processor Family Hardware Manual
Figure 28: NAND Flash Program Timing Diagram.............................................................................................64
Figure 29: NAND Flash Erase Timing Diagram .................................................................................................65
Figure 30: NAND Flash Small Block Read Timing Diagram ..............................................................................65
Figure 31: NAND Flash Large Block Read Timing Diagram..............................................................................66
Figure 32: NAND Flash Status Read Timing Diagram.......................................................................................66
Figure 33: NAND Flash ID Read Timing Diagram .............................................................................................67
Figure 34: NAND Flash Reset Timing Diagram .................................................................................................67
Figure 35: MultiMedia Card Timing Diagrams....................................................................................................69
Figure 36: Smart Panel Interface 8-bit 8080-Series Parallel Mode Read Interface Protocol.............................71
Figure 37: Smart Panel Interface 8-bit 8080-Series Parallel Mode Write Interface Protocol .............................71
Figure 38: Smart Panel Interface 8-bit 6800-Series Parallel Mode Read Interface Protocol.............................72
Figure 39: Smart Panel Interface 8-bit 6800-Series Parallel Mode Write Interface Protocol .............................72
Figure 40: SPI Write/Read Protocol...................................................................................................................73
Figure 41: Dumb LCD Panel Horizontal Timing.................................................................................................74
Figure 42: Dumb LCD Panel Vertical Timing .....................................................................................................74
Figure 43: Parallel Timing Diagram ...................................................................................................................76
Figure 44: SSP Master Mode Timing Diagram ..................................................................................................77
Figure 45: SSP Slave Mode Timing Definitions .................................................................................................78
Figure 46: TWSI Output Delay AC Timing Diagram...........................................................................................79
Figure 47: TWSI Output Delay AC Timing Diagram...........................................................................................79
Figure 48: TWSI Test Circuit..............................................................................................................................81
Figure 49: AC’97 CODEC Timing Diagram........................................................................................................82
Figure 50: JTAG Interface Output Delay AC Timing Diagram ...........................................................................83
Figure 51: JTAG Interface Input AC Timing Diagram ........................................................................................83
Figure 52: JTAG Interface Test Circuit ..............................................................................................................84
Figure 53: Low/Full Speed Data Signal Rise and Fall Time ..............................................................................85
Figure 54: High Speed TX Eye Diagram Pattern Template ...............................................................................85
Figure 55: High Speed RX Eye Diagram Pattern Template...............................................................................86
Figure 56: MII Tx Mode Interface Timing Diagrams...........................................................................................90
Figure 57: MII Rx Model Interface Timing Diagrams..........................................................................................91
Figure 58: MII Management Interface Timing Diagrams....................................................................................91
Figure 59: Power-Up Reset Timing....................................................................................................................94
Figure 60: Powerdown Timing ...........................................................................................................................96
8 Design Guidelines and Checklist ................................................................................................... 97
Figure 61: Panel Power Sequence ..................................................................................................................100
Figure 62: DPOT Programming Sequence ......................................................................................................101
Figure 63: Source Driver Connections.............................................................................................................102
Figure 64: Source Driver Timing ......................................................................................................................103
Figure 65: Gate Driver Connections ................................................................................................................104
Figure 66: Gate Driver Output Enable Timing..................................................................................................104
Doc. No. MV-S301545-00 Rev. - Copyright © 2010 Marvell
Page 8
November 2010 PUBLIC RELEASE