Hardware/Software Introduction Chapter 1 Introduction

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Losses due to delayed market entry Peak revenue • Simplified revenue model – Product life = 2W, peak at W Revenues ($) Market rise On-time Peak revenue from delayed entry Market fall – Time of market entry defines a triangle, representing market penetration Delayed – Triangle area equals revenue • Loss D On-time Delayed entry entry W Time 2W – The difference between the ontime and delayed triangle areas Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis 12
Losses due to delayed market entry (cont.) • Area = 1/2 * base * height Peak revenue – On-time = 1/2 * 2W * W Revenues ($) Market rise On-time Peak revenue from delayed entry Market fall – Delayed = 1/2 * (W-D+W)*(W-D) • Percentage revenue loss = (D(3W-D)/2W 2 )*100% Delayed • Try some examples D On-time Delayed entry entry W Time 2W – Lifetime 2W=52 wks, delay D=4 wks – (4*(3*26 –4)/2*26^2) = 22% – Lifetime 2W=52 wks, delay D=10 wks – (10*(3*26 –10)/2*26^2) = 50% – Delays are costly! Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis 13
Page 1 and 2: Embedded Systems Design: A Unified
Page 3 and 4: Embedded systems overview • Embed
Page 5 and 6: Some common characteristics of embe
Page 7 and 8: Design challenge - optimizing desig
Page 9 and 10: Design challenge - optimizing desig
Page 11: Time-to-market: a demanding design
Page 15 and 16: The performance design metric • W
Page 17 and 18: Processor technology • The archit
Page 19 and 20: General-purpose processors • Prog
Page 21 and 22: Application-specific processors •
Page 23 and 24: Full-custom/VLSI • All layers are
Page 25 and 26: PLD (Programmable Logic Device) •
Page 27 and 28: Graphical illustration of Moore’s
Page 29 and 30: The co-design ladder • In the pas
Page 31 and 32: Design productivity gap • 1981 le
Page 33 and 34: Summary • Embedded systems are ev
Page 35 and 36: Ch3. GPP: Software Summary • Gene
Page 37 and 38: Ch7. Digital Camera Example Summary
Page 39 and 40: Embedded Systems Design: A Unified
Page 41 and 42: Introduction • Design task - Defi
Page 43 and 44: Automation: synthesis • Early des
Page 45 and 46: Increasing abstraction level • Hi
Page 47 and 48: Gajski’s Y-chart • Each axis re
Page 49 and 50: Two-level minimization • Represen
Page 51 and 52: Minimum cover: K-map approach • K
Page 53 and 54: Minimum cover: heuristics • K-map
Page 55 and 56: Example • Minimized 2-level logic
Page 57 and 58: Technology mapping • Library of g
Page 59 and 60: Integrating logic design and physic
Page 61 and 62: Behavioral synthesis • High-level
Page 63 and 64:
System synthesis • Tasks (cont.)
Page 65 and 66:
Temporal vs. spatial thinking • D
Page 67 and 68:
Verification • Ensuring design is
Page 69 and 70:
Simulation • Create computer mode
Page 71 and 72:
Advantages over physical implementa
Page 73 and 74:
Simulation speed • Relative speed
Page 75 and 76:
Reducing precision/accuracy • Don
Page 77 and 78:
Integrating GPP/SPP simulations •
Page 79 and 80:
Emulators • General physical devi
Page 81 and 82:
Reuse: intellectual property cores
Page 83 and 84:
Advantages/disadvantages of hard co
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New challenges to processor provide
Page 87 and 88:
New challenges to processor users
Page 89 and 90:
Waterfall method • Not very reali
Page 91 and 92:
General-purpose processor design mo
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Summary • Design technology seeks
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Hardware/Software Introduction Chapter 1 Introduction

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