Hardware/Software Introduction Chapter 1 Introduction

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Minimizing communication • Memory shared between GPP and SPPs – Where should memory go? – In ISS • HDL simulator must stall for memory access – In HDL? • ISS must stall when fetching each instruction • Model memory in both ISS and HDL – Most accesses by each model unrelated to other’s accesses • No need to communicate these between models – Co-simulator ensures consistency of shared data – Huge speedups (100x or more) reported with this technique Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis 78
Emulators • General physical device system mapped to – Microprocessor emulator • Microprocessor IC with some monitoring, control circuitry – SPP emulator • FPGAs (10s to 100s) – Usually supports debugging tasks • Created to help solve simulation disadvantages – Mapped relatively quickly • Hours, days – Can be placed in real environment • No environment setup time • No incomplete environment – Typically faster than simulation • Hardware implementation Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis 79
Page 1 and 2:
Embedded Systems Design: A Unified
Page 3 and 4:
Embedded systems overview • Embed
Page 5 and 6:
Some common characteristics of embe
Page 7 and 8:
Design challenge - optimizing desig
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Design challenge - optimizing desig
Page 11 and 12:
Time-to-market: a demanding design
Page 13 and 14:
Losses due to delayed market entry
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The performance design metric • W
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Processor technology • The archit
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General-purpose processors • Prog
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Application-specific processors •
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Full-custom/VLSI • All layers are
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PLD (Programmable Logic Device) •
Page 27 and 28: Graphical illustration of Moore’s
Page 29 and 30: The co-design ladder • In the pas
Page 31 and 32: Design productivity gap • 1981 le
Page 33 and 34: Summary • Embedded systems are ev
Page 35 and 36: Ch3. GPP: Software Summary • Gene
Page 37 and 38: Ch7. Digital Camera Example Summary
Page 39 and 40: Embedded Systems Design: A Unified
Page 41 and 42: Introduction • Design task - Defi
Page 43 and 44: Automation: synthesis • Early des
Page 45 and 46: Increasing abstraction level • Hi
Page 47 and 48: Gajski’s Y-chart • Each axis re
Page 49 and 50: Two-level minimization • Represen
Page 51 and 52: Minimum cover: K-map approach • K
Page 53 and 54: Minimum cover: heuristics • K-map
Page 55 and 56: Example • Minimized 2-level logic
Page 57 and 58: Technology mapping • Library of g
Page 59 and 60: Integrating logic design and physic
Page 61 and 62: Behavioral synthesis • High-level
Page 63 and 64: System synthesis • Tasks (cont.)
Page 65 and 66: Temporal vs. spatial thinking • D
Page 67 and 68: Verification • Ensuring design is
Page 69 and 70: Simulation • Create computer mode
Page 71 and 72: Advantages over physical implementa
Page 73 and 74: Simulation speed • Relative speed
Page 75 and 76: Reducing precision/accuracy • Don
Page 77: Integrating GPP/SPP simulations •
Page 81 and 82: Reuse: intellectual property cores
Page 83 and 84: Advantages/disadvantages of hard co
Page 85 and 86: New challenges to processor provide
Page 87 and 88: New challenges to processor users
Page 89 and 90: Waterfall method • Not very reali
Page 91 and 92: General-purpose processor design mo
Page 93 and 94: Summary • Design technology seeks
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Hardware/Software Introduction Chapter 1 Introduction

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