Hardware/Software Introduction Chapter 1 Introduction

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Disadvantages • Still not as fast as real implementations – E.g., emulated cruise-control may not respond fast enough to keep control of car • Mapping still time consuming – E.g., mapping complex SOC to 10 FPGAs • Just partitioning into 10 parts could take weeks • Can be very expensive – Top-of-the-line FPGA-based emulator: $100,000 to $1mill – Leads to resource bottleneck • Can maybe only afford 1 emulator • Groups wait days, weeks for other group to finish using Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis 80
Reuse: intellectual property cores • Commercial off-the-shelf (COTS) components – Predesigned, prepackaged ICs – Implements GPP or SPP – Reduces design/debug time – Have always been available • System-on-a-chip (SOC) – All components of system implemented on single chip – Made possible by increasing IC capacities – Changing the way COTS components sold • As intellectual property (IP) rather than actual IC – Behavioral, structural, or physical descriptions – Processor-level components known as cores • SOC built by integrating multiple descriptions Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis 81
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Embedded Systems Design: A Unified
Page 3 and 4:
Embedded systems overview • Embed
Page 5 and 6:
Some common characteristics of embe
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Design challenge - optimizing desig
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Design challenge - optimizing desig
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Time-to-market: a demanding design
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Losses due to delayed market entry
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The performance design metric • W
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Processor technology • The archit
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General-purpose processors • Prog
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Application-specific processors •
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Full-custom/VLSI • All layers are
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PLD (Programmable Logic Device) •
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Graphical illustration of Moore’s
Page 29 and 30: The co-design ladder • In the pas
Page 31 and 32: Design productivity gap • 1981 le
Page 33 and 34: Summary • Embedded systems are ev
Page 35 and 36: Ch3. GPP: Software Summary • Gene
Page 37 and 38: Ch7. Digital Camera Example Summary
Page 39 and 40: Embedded Systems Design: A Unified
Page 41 and 42: Introduction • Design task - Defi
Page 43 and 44: Automation: synthesis • Early des
Page 45 and 46: Increasing abstraction level • Hi
Page 47 and 48: Gajski’s Y-chart • Each axis re
Page 49 and 50: Two-level minimization • Represen
Page 51 and 52: Minimum cover: K-map approach • K
Page 53 and 54: Minimum cover: heuristics • K-map
Page 55 and 56: Example • Minimized 2-level logic
Page 57 and 58: Technology mapping • Library of g
Page 59 and 60: Integrating logic design and physic
Page 61 and 62: Behavioral synthesis • High-level
Page 63 and 64: System synthesis • Tasks (cont.)
Page 65 and 66: Temporal vs. spatial thinking • D
Page 67 and 68: Verification • Ensuring design is
Page 69 and 70: Simulation • Create computer mode
Page 71 and 72: Advantages over physical implementa
Page 73 and 74: Simulation speed • Relative speed
Page 75 and 76: Reducing precision/accuracy • Don
Page 77 and 78: Integrating GPP/SPP simulations •
Page 79: Emulators • General physical devi
Page 83 and 84: Advantages/disadvantages of hard co
Page 85 and 86: New challenges to processor provide
Page 87 and 88: New challenges to processor users
Page 89 and 90: Waterfall method • Not very reali
Page 91 and 92: General-purpose processor design mo
Page 93 and 94: Summary • Design technology seeks
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