Hardware/Software Introduction Chapter 1 Introduction

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Multilevel logic minimization • Trade performance for size – Increase delay for lower # of gates – Gray area represents all possible solutions – Circle with X represents ideal solution • Generally not possible – 2-level gives best performance • max delay = 2 gates • Solve for smallest size – Multilevel gives pareto-optimal solution • Minimum delay for a given size • Minimum size for a given delay delay multi-level minim. 2-level minim. size Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis 54
Example • Minimized 2-level logic function: – F = adef + bdef + cdef + gh – Requires 5 gates with 18 total gate inputs • 4 ANDS and 1 OR • After algebraic manipulation: – F = (a + b + c)def + gh – Requires only 4 gates with 11 total gate inputs • 2 ANDS and 2 ORs – Less inputs per gate – Assume gate inputs = 2 transistors • Reduced by 14 transistors – 36 (18 * 2) down to 22 (11 * 2) – Sacrifices performance for size • Inputs a, b, and c now have 3-gate delay • Iterative improvement heuristic commonly used a d b e c f g h 2-level minimized multilevel minimized a b c d e f g F h F Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis 55
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Embedded Systems Design: A Unified
Page 3 and 4: Embedded systems overview • Embed
Page 5 and 6: Some common characteristics of embe
Page 7 and 8: Design challenge - optimizing desig
Page 9 and 10: Design challenge - optimizing desig
Page 11 and 12: Time-to-market: a demanding design
Page 13 and 14: Losses due to delayed market entry
Page 15 and 16: The performance design metric • W
Page 17 and 18: Processor technology • The archit
Page 19 and 20: General-purpose processors • Prog
Page 21 and 22: Application-specific processors •
Page 23 and 24: Full-custom/VLSI • All layers are
Page 25 and 26: PLD (Programmable Logic Device) •
Page 27 and 28: Graphical illustration of Moore’s
Page 29 and 30: The co-design ladder • In the pas
Page 31 and 32: Design productivity gap • 1981 le
Page 33 and 34: Summary • Embedded systems are ev
Page 35 and 36: Ch3. GPP: Software Summary • Gene
Page 37 and 38: Ch7. Digital Camera Example Summary
Page 39 and 40: Embedded Systems Design: A Unified
Page 41 and 42: Introduction • Design task - Defi
Page 43 and 44: Automation: synthesis • Early des
Page 45 and 46: Increasing abstraction level • Hi
Page 47 and 48: Gajski’s Y-chart • Each axis re
Page 49 and 50: Two-level minimization • Represen
Page 51 and 52: Minimum cover: K-map approach • K
Page 53: Minimum cover: heuristics • K-map
Page 57 and 58: Technology mapping • Library of g
Page 59 and 60: Integrating logic design and physic
Page 61 and 62: Behavioral synthesis • High-level
Page 63 and 64: System synthesis • Tasks (cont.)
Page 65 and 66: Temporal vs. spatial thinking • D
Page 67 and 68: Verification • Ensuring design is
Page 69 and 70: Simulation • Create computer mode
Page 71 and 72: Advantages over physical implementa
Page 73 and 74: Simulation speed • Relative speed
Page 75 and 76: Reducing precision/accuracy • Don
Page 77 and 78: Integrating GPP/SPP simulations •
Page 79 and 80: Emulators • General physical devi
Page 81 and 82: Reuse: intellectual property cores
Page 83 and 84: Advantages/disadvantages of hard co
Page 85 and 86: New challenges to processor provide
Page 87 and 88: New challenges to processor users
Page 89 and 90: Waterfall method • Not very reali
Page 91 and 92: General-purpose processor design mo
Page 93 and 94: Summary • Design technology seeks
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Hardware/Software Introduction Chapter 1 Introduction

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