128-Bit Addressing in RISC-V and Security

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PresentaCon • Background/FoundaConal NoCons – From the 1970’s to today • Exascale Issues • Proposal (Strawman) • ProtecCon structures for current address spaces • References 2016 _NOV _RISCV_WORKSHOP 2
Background • Since the late 70’s, mainstream processors have increased the size of the virtual space by simply adding more bits – DEC PDP/11 & VAX: 16è 32 – Data General Eclipse/MV: 16 è 32 – SPARC & HP RISC: 32 è 64 – Intel x86; 16è 32 è 64 (48 used) • Itanium 64 – IBM Power: 32 è 64 – ARM: 32 è 64 • Memory management and protecCon are intermingled 2016 _NOV _RISCV_WORKSHOP 3
Page 1: 128-Bit Addressing in RISC-V and Se
Page 5 and 6: What Happened • MulCcs at MIT - U
Page 7 and 8: Going Forward • There Time is to
Page 9 and 10: ProtecCon ObjecCves • The origina
Page 11 and 12: Previous Efforts • Another soluCo
Page 13 and 14: Strawman - RV128I OBJECT ID Byte Of
Page 15 and 16: What is a Object ? • A Object is
Page 17 and 18: AuthenCcaCon • The address space
Page 19 and 20: Memory Management • Each object c
Page 21 and 22: 64 BIT LINUX -Memory Management Pro
Page 23 and 24: Exascale Issues • Subject to cost
Page 25 and 26: 128- BIT VIRTUAL ADDRESSING -Protec
Page 27 and 28: ACL (Access Control List) - ENTRY P
Page 29 and 30: REFERENCE MONITOR • It must valid
Page 31 and 32: Summary • Compare to CHERI [12] -
Page 33 and 34: References • [12] Robert N.M. Wat
Page 35 and 36: RevocaCon • Every client has a
Page 37 and 38: Some Object UID Math • 60 seconds
Page 39 and 40: ProtecCon in Unified Name Space •
Page 41: Shadow Stack - Architecture Return

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