128-Bit Addressing in RISC-V and Security
Tue1530-128bit-Addr-RISC-V-Wallach-Micron
Tue1530-128bit-Addr-RISC-V-Wallach-Micron
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Background<br />
• S<strong>in</strong>ce the late 70’s, ma<strong>in</strong>stream<br />
processors have <strong>in</strong>creased the<br />
size of the virtual space by simply<br />
add<strong>in</strong>g more bits<br />
– DEC PDP/11 & VAX: 16è 32<br />
– Data General Eclipse/MV: 16 è 32<br />
– SPARC & HP <strong>RISC</strong>: 32 è 64<br />
– Intel x86; 16è 32 è 64 (48 used)<br />
• Itanium 64<br />
– IBM Power: 32 è 64<br />
– ARM: 32 è 64<br />
• Memory management <strong>and</strong><br />
protecCon are <strong>in</strong>term<strong>in</strong>gled<br />
2016 _NOV _<strong>RISC</strong>V_WORKSHOP<br />
3
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