Contents - Freescale Semiconductor

Contents
Paragraph
Number Title
Chapter 14
DMA Engine 2
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual, Rev. 0
Page
Number
14.1 DMA Features................................................................................................................ 14-1
14.2 DMA Memory Map/Register Definition ....................................................................... 14-2
14.3 DMA Register Descriptions........................................................................................... 14-3
14.3.1 DMA Registers .......................................................................................................... 14-3
14.4 Functional Description................................................................................................... 14-9
14.4.1 DMA Operation ......................................................................................................... 14-9
14.4.2 DMA Segment Descriptors...................................................................................... 14-10
14.5 Initialization/Application Information......................................................................... 14-12
14.5.1 Initialization Steps in Direct Mode.......................................................................... 14-12
14.5.2 Initialization Steps in Chaining Mode ..................................................................... 14-13
Chapter 15
FlexCAN
15.1 Introduction.................................................................................................................... 15-1
15.1.1 Overview.................................................................................................................... 15-2
15.1.2 FlexCAN Module Features........................................................................................ 15-3
15.1.3 Modes of Operation ................................................................................................... 15-4
15.2 External Signal Description ........................................................................................... 15-5
15.2.1 Signals Overview....................................................................................................... 15-5
15.3 Memory Map/Register Definition ................................................................................. 15-5
15.3.1 Message Buffer Structure .......................................................................................... 15-7
15.3.2 Rx FIFO Structure ................................................................................................... 15-10
15.3.3 Register Descriptions............................................................................................... 15-12
15.4 Functional Description................................................................................................. 15-28
15.4.1 Overview.................................................................................................................. 15-28
15.4.2 Transmit Process...................................................................................................... 15-29
15.4.3 Arbitration process................................................................................................... 15-30
15.4.4 Receive Process ....................................................................................................... 15-30
15.4.5 Matching Process..................................................................................................... 15-32
15.4.6 Data Coherence....................................................................................................... 15-33
15.4.7 Rx FIFO ................................................................................................................... 15-36
15.4.8 CAN Protocol Related Features............................................................................... 15-36
15.4.9 Modes of Operation Details..................................................................................... 15-40
15.4.10 WInterrupts .............................................................................................................. 15-41
15.4.11 Bus Interface............................................................................................................ 15-42
15.5 Initialization/Application Information......................................................................... 15-42
15.5.1 FlexCAN Initialization Sequence ............................................................................ 15-42
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