Contents - Freescale Semiconductor

Figures
Figure
Number Title
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual, Rev. 0
Page
Number
11-34 GPCM Basic Write Timing
(XACS = 0, ACS = 00, CSNT = 1, SCY = 1, TRLX = 0, CLKDIV = 4, 8).................. 11-48
11-35 GPCM Relaxed Timing Back-to-Back Reads
(XACS = 0, ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1, EHTR = 0, CLKDIV = 4, 8)11-50
11-36 GPCM Relaxed Timing Back-to-Back Writes
(XACS = 0, ACS = 1x, SCY = 0, CSNT = 0, TRLX = 1, CLKDIV = 4, 8).................. 11-50
11-37 GPCM Relaxed Timing Write
(XACS = 0, ACS = 10, SCY = 0, CSNT = 1, TRLX = 1, CLKDIV = 4, 8).................. 11-51
11-38 GPCM Relaxed Timing Write
(XACS = 0, ACS = 00, SCY = 1, CSNT = 1, TRLX = 1, CLKDIV = 4, 8).................. 11-51
11-39 GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing)......................... 11-52
11-40 GPCM Read Followed by Write
(TRLX = 0, EHTR = 1, One-Cycle Extended Hold Time on Reads) ............................ 11-53
11-41 External Termination of GPCM Access (PLL Bypass Mode)............................................ 11-54
11-42 Local Bus to 8-Bit FCM Device Interface .......................................................................... 11-56
11-43 FCM Basic Page Read Timing
(PGS = 1, CSCT = 0, CST = 0, CHT = 1, RST = 1, SCY = 0, TRLX = 0, EHTR = 1) 11-57
11-44 FCM Buffer RAM Memory Map for Small-Page (512-Byte Page) NAND Flash Devices 11-59
11-45 FCM Buffer RAM Memory Map for Large-Page (2-Kbyte Page) NAND Flash Devices. 11-60
11-46 FCM ECC Calculation........................................................................................................ 11-60
11-47 ECC Placement in NAND Flash Spare Regions in Relation to FMR[ECCM] .................. 11-61
11-48 FCM Instruction Sequencer Mechanism............................................................................. 11-62
11-49 Timing of FCM Command/Address and Write Data Cycles
(for TRLX = 0, CHT = 0, CST = 1, SCY = 1, CLKDIV = 4*N)................................... 11-65
11-50 Example of FCM Command and Address Timing with Minimum Delay Parameters
(for TRLX = 0, CHT = 0, CST = 0, SCY = 0, CLKDIV = 4*N)................................... 11-66
11-51 Example of FCM Command and Address Timing with Relaxed Parameters
(for TRLX = 1, CHT = 0, CST = 1, SCY = 2, CLKDIV = 4*N)................................... 11-66
11-52 FCM Delay Prior to Sampling LFRB State ........................................................................ 11-67
11-53 FCM Read Data Timing
(for TRLX = 0, RST = 0, SCY = 1, CLKDIV = 4*N)................................................... 11-67
11-54 FCM Read Data Timing with Extended Hold Time
(for TRLX = 0, EHTR = 1, RST = 1, SCY = 1, CLKDIV = 4*N) ................................ 11-68
11-55 FCM Buffer RAM Memory Map During Boot Loading .................................................... 11-70
11-56 User-Programmable Machine Functional Block Diagram.................................................. 11-71
11-57 RAM Array Indexing .......................................................................................................... 11-72
11-58 Memory Refresh Timer Request Block Diagram ............................................................... 11-73
11-59 UPM Clock Scheme for LCRR[CLKDIV] = 2................................................................... 11-77
11-60 UPM Clock Scheme for LCRR[CLKDIV] = 4 or 8 ........................................................... 11-77
11-61 RAM Array and Signal Generation .................................................................................... 11-77
11-62 RAM Word Fields ............................................................................................................... 11-78
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