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Figure
Number Title
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual, Rev. 0
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12-27 Flow Chart for Reset of eSDHC and SD I/O Card ............................................................. 12-49
13-1 DMA Block Diagram............................................................................................................ 13-1
13-2 DMA Control Register (DMACR) ....................................................................................... 13-4
13-3 DMA Error Status Register (DMAES) ................................................................................. 13-7
13-4 DMA Enable Request Register (DMAERQ) ........................................................................ 13-9
13-5 DMA Enable Error Interrupt Register (DMAEEI) ............................................................. 13-10
13-6 DMA Set Enable Request Register..................................................................................... 13-10
13-7 DMA Clear Enable Request Register ................................................................................. 13-11
13-8 DMA Set Enable Error Interrupt Register .......................................................................... 13-12
13-9 DMA Clear Enable Error Interrupt Register....................................................................... 13-12
13-10 DMA Clear Interrupt Request Register .............................................................................. 13-13
13-11 DMA Clear Error Register.................................................................................................. 13-14
13-12 DMA Set START Bit Register............................................................................................ 13-14
13-13 DMA Clear DONE Status Register..................................................................................... 13-15
13-14 DMA Interrupt Request Register Low (DMAINT) ............................................................ 13-16
13-15 DMA Error Register (DMAERR)....................................................................................... 13-17
13-16 DMA General Purpose Output Register (DMAGPOR)...................................................... 13-17
13-17 DMA Clear DONE Status Register..................................................................................... 13-19
13-18 TCD Word 0 (TCDn.saddr) Field ....................................................................................... 13-20
13-19 TCD Word 1 (TCDn.{soff, smod, ssize, dmod, dsize}) Fields........................................... 13-21
13-20 TCD Word 2 (TCDn.nbytes) Field...................................................................................... 13-22
13-21 TCD Word 3 (TCDn.slast) Field......................................................................................... 13-22
13-22 TCD Word 4 (TCDn.daddr) Field....................................................................................... 13-23
13-23 TCD Word 5 (TCDn.{citer, doff}) Fields ........................................................................... 13-23
13-24 TCD Word 6 (TCDn.dlast_sga) Field ................................................................................. 13-24
13-25 TCD Word 7 (TCDn.{biter, control/status]) Fields ............................................................ 13-25
13-26 DMA Operation—Part 1..................................................................................................... 13-29
13-27 DMA Operation—Part 2..................................................................................................... 13-30
13-28 DMA Operation—Part 3..................................................................................................... 13-31
14-1 DMA Engine 2 Block Diagram ............................................................................................ 14-1
14-2 DMA Mode Register (DMAMRn) ....................................................................................... 14-3
14-3 DMA Status Register (DMASRn) ........................................................................................ 14-5
14-4 DMA Current Descriptor Address Register (DMACDARn)................................................ 14-6
14-5 DMA Source Address Register (DMASARn) ...................................................................... 14-7
14-6 DMA Destination Address Register (DMADARn) .............................................................. 14-7
14-7 DMA Byte Count Register (DMABCRn)............................................................................. 14-8
14-8 DMA Next Descriptor Address Register (DMANDARn).................................................... 14-8
14-9 DMA General Status Register (DMAGSR).......................................................................... 14-9
14-10 DMA Chain of Segment Descriptors .................................................................................. 14-11
15-1 FlexCAN Block Diagram...................................................................................................... 15-2
15-2 Message Buffer Structure...................................................................................................... 15-7
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