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Figures
Figure
Number Title
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual, Rev. 0
Page
Number
6-8 System General Purpose Register Low (SGPRL)................................................................. 6-13
6-9 System General Purpose Register High (SGPRH) ............................................................... 6-14
6-10 System Part and Revision ID Register (SPRIDR) ................................................................ 6-14
6-11 System Priority Configuration Register (SPCR) .................................................................. 6-16
6-12 System I/O Configuration Register 1 (SICR_1) ................................................................... 6-17
6-13 System I/O Configuration Register 2 (SICR_2) ................................................................... 6-22
6-14 System I/O Configuration Register 3 (SICR_3) ................................................................... 6-26
6-15 System I/O Delay Configuration Register (SIDCR0–1)....................................................... 6-27
6-16 DDR Control Driver Register (DDRCDR)........................................................................... 6-31
6-17 DDR Debug Status Register (DDRDSR).............................................................................. 6-32
6-18 eSDHC Control Register (SDHCCR) ................................................................................... 6-33
6-19 CAN Access Control Register (CAN_DBG_CTRL)............................................................ 6-35
6-20 General Purpose Register 1 (GPR_1) ................................................................................... 6-36
6-21 CAN Interrupt Status Register (CAN_INT_STAT) .............................................................. 6-39
6-22 DUART Interrupt Status Register (DUART_INT_STAT) .................................................... 6-41
6-23 GPIO Interrupt Status Register (GPIO_INT_STAT) ............................................................ 6-42
6-24 Software Watchdog Timer High-Level Block Diagram ....................................................... 6-44
6-25 System Watchdog Control Register (SWCRR)..................................................................... 6-45
6-26 System Watchdog Count Register (SWCNR)....................................................................... 6-46
6-27 System Watchdog Service Register (SWSRR) ..................................................................... 6-47
6-28 Software Watchdog Timer Service State Diagram................................................................ 6-48
6-29 Software Watchdog Timer Functional Block Diagram......................................................... 6-49
6-30 Real Time Clock Module High Level Block Diagram ......................................................... 6-51
6-31 Real Time Counter Control Register (RTCNR).................................................................... 6-52
6-32 Real Time Counter Load Register (RTLDR) ........................................................................ 6-53
6-33 Real Time Counter Prescale Register (RTPSR).................................................................... 6-54
6-34 Real Time Counter Register (RTCTR).................................................................................. 6-54
6-35 Real Time Counter Event Register (RTEVR)....................................................................... 6-55
6-36 Real Time Counter Alarm Register (RTALR) ...................................................................... 6-55
6-37 Real Time Clock Module Functional Block Diagram .......................................................... 6-56
6-38 Periodic Interval Timer High Level Block Diagram............................................................. 6-58
6-39 Periodic Interval Timer Control Register (PTCNR) ............................................................. 6-59
6-40 Periodic Interval Timer Load Register (PTLDR).................................................................. 6-60
6-41 Periodic Interval Timer Prescale Register (PTPSR) ............................................................. 6-61
6-42 Periodic Interval Timer Counter Register (PTCTR) ............................................................. 6-61
6-43 Periodic Interval Timer Event Register (PTEVR)................................................................. 6-62
6-44 Periodic Interval Timer Functional Block Diagram.............................................................. 6-63
6-45 Global Timers Block Diagram .............................................................................................. 6-64
6-46 Global Timers Configuration Register 1 (GTCFR1)............................................................. 6-69
6-47 Global Timers Configuration Register 2 (GTCFR2)............................................................. 6-71
6-48 Global Timers Mode Registers (GTMDR1–GTMDR4)........................................................ 6-72
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