Contents - Freescale Semiconductor

Tables
Table
Number Title
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual, Rev. 0
Page
Number
4-30 System PLL Mode Register Bit Settings .............................................................................. 4-31
4-31 OCCR Bit Settings ................................................................................................................ 4-32
4-32 SCCR Bit Descriptions ......................................................................................................... 4-33
5-1 Boot Source Selection for On-Chip ROM Boot- RCWHR Settings ...................................... 5-1
5-2 SD/MMC Card Data Structure................................................................................................ 5-4
5-3 Config Address Field Description, CNT = 0 .......................................................................... 5-6
5-4 Config Address Field Description, CNT = 1 .......................................................................... 5-6
5-5 SPI EEPROM Data Structure................................................................................................ 5-12
5-6 Config Address Field Description, CNT = 0 ........................................................................ 5-14
5-7 Config Address Field Description, CNT = 1 ........................................................................ 5-14
6-1 Local Access Windows Target Interface................................................................................. 6-1
6-2 Local Access Windows Example............................................................................................ 6-2
6-3 Format of Window Definitions ............................................................................................... 6-3
6-4 Local Access Register Memory Map...................................................................................... 6-4
6-5 IMMRBAR Bit Settings.......................................................................................................... 6-6
6-6 ALTCBAR Bit Settings........................................................................................................... 6-7
6-7 LBLAWBAR0–LBLAWBAR3 Bit Settings........................................................................... 6-7
6-8 LBLAWBAR0[BASE_ADDR] Reset Value .......................................................................... 6-8
6-9 LBLAWAR0–LBLAWAR3 Bit Settings................................................................................. 6-8
6-10 LBLAWAR0[EN] Reset Value................................................................................................ 6-9
6-11 DDRLAWBAR0–DDRLAWBAR1 Bit Settings.................................................................... 6-9
6-12 DDRLAWBAR0[BASE_ADDR] Reset Value ..................................................................... 6-10
6-13 DDRLAWAR0–DDRLAWAR1 Bit Settings ........................................................................ 6-10
6-14 DDRLAWAR0[EN] Reset Value .......................................................................................... 6-11
6-15 Overlapping Local Access Windows .................................................................................... 6-11
6-16 System Configuration Register Memory Map ...................................................................... 6-12
6-17 SGPRL Bit Settings .............................................................................................................. 6-14
6-18 SGPRH Bit Settings .............................................................................................................. 6-14
6-19 SPRIDR Bit Settings............................................................................................................. 6-15
6-20 PARTID Coding ................................................................................................................... 6-15
6-21 REVID Coding ..................................................................................................................... 6-15
6-22 SPCR Bit Settings ................................................................................................................. 6-16
6-23 SICR_1 Bit Settings for MPC8306....................................................................................... 6-17
6-24 SICR_1 Bit Settings for MPC8306S..................................................................................... 6-19
6-25 SICR_2 Bit Settings for MPC8306 and MPC8306S ............................................................ 6-23
6-26 SICR_3 Bit Settings for MPC8306 and MPC8306S ............................................................ 6-26
6-27 SIDCR0 Bit Settings ............................................................................................................. 6-28
6-28 SIDCR1 Bit Settings ............................................................................................................. 6-30
6-29 DDRCDR Field Descriptions................................................................................................ 6-31
6-30 DDRDSR Field Descriptions ................................................................................................ 6-32
6-31 SDHCCR Field Description.................................................................................................. 6-33
xxxiv Freescale Semiconductor