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Contents - Freescale Semiconductor
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Figures<br />
Figure<br />
Number Title<br />
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual, Rev. 0<br />
Page<br />
Number<br />
xxxii <strong>Freescale</strong> <strong>Semiconductor</strong>
Figures Figure Number Title MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual, Rev. 0 Page Number xxxii <strong>Freescale</strong> <strong>Semiconductor</strong>
Tables Table Number Title MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual, Rev. 0 Page Number i Acronyms and Abbreviated Terms............................................................................................. li 1-1 QUICC Engine Protocols...................................................................................................... 1-14 1-2 UCC Protocol Enablement in the QUICC Engine Block ..................................................... 1-15 2-1 IMMR Memory Map ..............................................................................................................2-2 3-1 MPC8306 Signal Reference by Functional Block .................................................................. 3-5 3-2 MPC8306 Signal Reference by Alphabetical Order ............................................................. 3-19 3-3 MPC8306S Signal Reference by Functional Block.............................................................. 3-35 3-4 MPC8306S Signal Reference in Alphabetical Order............................................................ 3-48 3-5 Output Signal States During System Reset........................................................................... 3-60 4-1 System Control Signals........................................................................................................... 4-1 4-2 External Clock Signals............................................................................................................ 4-2 4-3 Reset Causes ........................................................................................................................... 4-4 4-4 Reset Actions .......................................................................................................................... 4-5 4-5 Reset Configuration Words Source......................................................................................... 4-9 4-6 Selecting Reset Configuration Input Signals ........................................................................ 4-10 4-7 RCWLR Bit Settings............................................................................................................. 4-11 4-8 System PLL VCO Division................................................................................................... 4-12 4-9 System PLL Ratio ................................................................................................................. 4-13 4-10 QUICC Engine PLL Multiplication Factor........................................................................... 4-13 4-11 Reset Configuration Word High Bit Settings........................................................................ 4-14 4-12 Boot Memory Space.............................................................................................................. 4-15 4-13 Boot Sequencer Configuration ............................................................................................. 4-16 4-14 Boot ROM Location.............................................................................................................. 4-17 4-15 e300 Core True Little-Endian ............................................................................................... 4-17 4-16 Local Bus Configuration EEPROM Addresses .................................................................... 4-18 4-17 Local Bus Reset Configuration Words Data Structure.......................................................... 4-18 4-18 Local Bus Controller Setting when Loading RCW .............................................................. 4-19 4-19 RCW Values Corresponding to Hard Coded Options........................................................... 4-22 4-20 Hard Coded Reset Configuration Word Low Fields Values ................................................. 4-22 4-21 Hard-Coded Reset Configuration Word High Field Values.................................................. 4-23 4-22 Configurable Clock Units ..................................................................................................... 4-25 4-23 Reset Configuration and Status Registers Memory Map...................................................... 4-26 4-24 Reset Status Register Field Descriptions .............................................................................. 4-27 4-25 RMR Field Descriptions ....................................................................................................... 4-28 4-26 RPR Bit Descriptions ............................................................................................................ 4-29 4-27 RCR Bit Settings................................................................................................................... 4-30 4-28 RCER Bit Settings ................................................................................................................ 4-30 4-29 Clock Configuration Registers Memory Map....................................................................... 4-30 <strong>Freescale</strong> <strong>Semiconductor</strong> xxxiii
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- Page 3 and 4: Contents Paragraph Number Title Abo
- Page 5 and 6: Contents Paragraph Number Title MPC
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- Page 11 and 12: Contents Paragraph Number Title Cha
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- Page 35 and 36: Tables Table Number Title MPC8306 P
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- Page 41 and 42: Tables Table Number Title MPC8306 P
- Page 43 and 44: Tables Table Number Title MPC8306 P
- Page 45 and 46: Tables Table Number Title MPC8306 P
- Page 47 and 48: About This Book This reference manu
- Page 49 and 50: • Chapter 20, “JTAG/Testing Sup
- Page 51 and 52: Acronyms and Abbreviations Table i
- Page 53 and 54: RISC Reduced instruction set comput
- Page 55 and 56: Chapter 1 Overview This chapter pro
- Page 57 and 58: MPC8306 PowerQUICC II Pro Integrate
- Page 59 and 60: MPC8306 PowerQUICC II Pro Integrate
- Page 61 and 62: MPC8306 PowerQUICC II Pro Integrate
- Page 63 and 64: MPC8306 PowerQUICC II Pro Integrate
- Page 65 and 66: 1.3.2 QUICC Engine Block MPC8306 Po
- Page 67 and 68: • Some of the interfaces are mult
- Page 69 and 70: 1.3.2.6 QUICC Engine UCC Capabiliti
- Page 71 and 72: MPC8306 PowerQUICC II Pro Integrate
- Page 73 and 74: • Interrupt • Isochronous 1.3.7
- Page 75 and 76: 1.3.10 DMA Engine 1 MPC8306 PowerQU
- Page 77 and 78: Chapter 2 Memory Map This chapter d
- Page 79 and 80: 0x0_4B00-0x0_4FFF Reserved — 1.25
- Page 81 and 82: Chapter 3 Signal Descriptions This
- Page 83 and 84:
DDR2 Memory Interface 48 Signals eL
- Page 85 and 86:
MPC8306 PowerQUICC II Pro Integrate
- Page 87 and 88:
UART1_SOUT[1] DUART serial data out
- Page 89 and 90:
Table 3-1. MPC8306 Signal Reference
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Table 3-1. MPC8306 Signal Reference
- Page 93 and 94:
Table 3-1. MPC8306 Signal Reference
- Page 95 and 96:
HDLC2_TXCLK HDLC2 transmit clock HD
- Page 97 and 98:
MPC8306 PowerQUICC II Pro Integrate
- Page 99 and 100:
Table 3-2 lists the signals in alph
- Page 101 and 102:
Name Description FEC3_RX_DV FEC3 re
- Page 103 and 104:
Name Description GPIO[37] General p
- Page 105 and 106:
Name Description HDLC1_RTS HDLC1 re
- Page 107 and 108:
Name Description MPC8306 PowerQUICC
- Page 109 and 110:
Name Description SD_CD Card detecti
- Page 111 and 112:
Name Description Table 3-2. MPC8306
- Page 113 and 114:
DDR2 Memory Interface 48 Signals eL
- Page 115 and 116:
MPC8306 PowerQUICC II Pro Integrate
- Page 117 and 118:
Table 3-3. MPC8306S Signal Referenc
- Page 119 and 120:
Table 3-3. MPC8306S Signal Referenc
- Page 121 and 122:
Table 3-3. MPC8306S Signal Referenc
- Page 123 and 124:
Table 3-3. MPC8306S Signal Referenc
- Page 125 and 126:
QE_EXT_REQ_3 QUICC Engine external
- Page 127 and 128:
MPC8306 PowerQUICC II Pro Integrate
- Page 129 and 130:
Name Description Table 3-4. MPC8306
- Page 131 and 132:
Name Description GPIO[25] General p
- Page 133 and 134:
Name Description GPIO[61] General p
- Page 135 and 136:
Name Description LCS[6] LBC chip se
- Page 137 and 138:
Name Description QE_EXT_REQ_4 QUICC
- Page 139 and 140:
Name Description UART1_SOUT[1] DUAR
- Page 141 and 142:
Table 3-5. Output Signal States Dur
- Page 143 and 144:
Chapter 4 Reset, Clocking, and Init
- Page 145 and 146:
FEC1_TX_CLK, FEC2_TX_CLK, FEC3_TX_C
- Page 147 and 148:
Table 4-4 identifies the reset acti
- Page 149 and 150:
Figure 4-1 shows a timing diagram o
- Page 151 and 152:
Reset, Clocking, and Initialization
- Page 153 and 154:
4.3.2.1 Reset Configuration Word Lo
- Page 155 and 156:
4.3.2.1.2 System PLL Configuration
- Page 157 and 158:
Reset, Clocking, and Initialization
- Page 159 and 160:
Reset, Clocking, and Initialization
- Page 161 and 162:
Reset, Clocking, and Initialization
- Page 163 and 164:
Reset, Clocking, and Initialization
- Page 165 and 166:
Reset, Clocking, and Initialization
- Page 167 and 168:
Reset, Clocking, and Initialization
- Page 169 and 170:
4.5.1.3 Reset Status Register (RSR)
- Page 171 and 172:
4.5.1.5 Reset Protection Register (
- Page 173 and 174:
Reset, Clocking, and Initialization
- Page 175 and 176:
4.5.2.3 System Clock Control Regist
- Page 177 and 178:
Chapter 5 System boot This chapter
- Page 179 and 180:
MPC8306 PowerQUICC II Pro Integrate
- Page 181 and 182:
0x5C-0x5F Reserved 0x60-0x63 Execut
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MPC8306 PowerQUICC II Pro Integrate
- Page 185 and 186:
MPC8306 PowerQUICC II Pro Integrate
- Page 187 and 188:
MPC8306 PowerQUICC II Pro Integrate
- Page 189 and 190:
0x68-0x6B N. Number of Config Addre
- Page 191 and 192:
Figure 5-6 shows the external signa
- Page 193 and 194:
Chapter 6 System Configuration 6.1
- Page 195 and 196:
System Configuration In this exampl
- Page 197 and 198:
6.2.4 Local Access Register Descrip
- Page 199 and 200:
NOTE ALTCBAR is not considered a lo
- Page 201 and 202:
6.2.4.4.1 LBLAWAR0[EN] and LBLAWAR0
- Page 203 and 204:
6.2.4.6.1 DDRLAWAR0[EN] and DDRLAWA
- Page 205 and 206:
Local Memory Offset (Hex) System Co
- Page 207 and 208:
Table 6-19 defines the bit fields o
- Page 209 and 210:
Figure 6-12 shows SICR_1. System Co
- Page 211 and 212:
Table 6-23. SICR_1 Bit Settings for
- Page 213 and 214:
Table 6-24. SICR_1 Bit Settings for
- Page 215 and 216:
System Configuration Table 6-25 def
- Page 217 and 218:
Table 6-25. SICR_2 Bit Settings for
- Page 219 and 220:
6.3.2.9 6.3.2.10 Debug Configuratio
- Page 221 and 222:
Table 6-27. SIDCR0 Bit Settings (co
- Page 223 and 224:
12-14 USB_DELAY_C USBDR_STP 000 15-
- Page 225 and 226:
6.3.2.14 eSDHC Control Register (SD
- Page 227 and 228:
System Configuration The CAN access
- Page 229 and 230:
2 PULLUP_ CTRL_2 3 PULLUP_ CTRL_3 4
- Page 231 and 232:
System Configuration The CAN interr
- Page 233 and 234:
6.3.2.18 DUART Interrupt Status Reg
- Page 235 and 236:
System Configuration — LCLK1 and
- Page 237 and 238:
6.4.4 WDT Memory Map/Register Defin
- Page 239 and 240:
Table 6-39 defines the bit fields o
- Page 241 and 242:
System Configuration Although most
- Page 243 and 244:
System Configuration register (RTCT
- Page 245 and 246:
Table 6-43 defines the bit fields o
- Page 247 and 248:
6.5.5.5 Real Time Counter Event Reg
- Page 249 and 250:
System Configuration — RTC enable
- Page 251 and 252:
Table 6-50 describes the external P
- Page 253 and 254:
6.6.5.3 Periodic Interval Timer Pre
- Page 255 and 256:
Figure 6-44shows the functional PIT
- Page 257 and 258:
System Configuration • Two timers
- Page 259 and 260:
System Configuration TGATE1 TGATE1
- Page 261 and 262:
System Configuration 0x020 Timer 3
- Page 263 and 264:
The GTCFR2 register is shown in Fig
- Page 265 and 266:
Table 6-62 defines the bit fields o
- Page 267 and 268:
System Configuration GTCNRn[CNV] fi
- Page 269 and 270:
6.7.6 Functional Description System
- Page 271 and 272:
System Configuration • Pair-casca
- Page 273 and 274:
6.8.1 External Signal Description T
- Page 275 and 276:
System Mode Low Power (PMCCR[SLPEN]
- Page 277 and 278:
Chapter 7 Arbiter and Bus Monitor T
- Page 279 and 280:
7.2.1 Arbiter Configuration Registe
- Page 281 and 282:
Table 7-3 describes ATR fields. 7.2
- Page 283 and 284:
29 AO Address only transfer type. T
- Page 285 and 286:
11-15 MSTR_ID Master Id. 00000 e300
- Page 287 and 288:
7.3 Functional Description The foll
- Page 289 and 290:
Z Y X Level 3 Figure 7-10. An Examp
- Page 291 and 292:
Arbiter and Bus Monitor 3. Issues r
- Page 293 and 294:
• Section 7.2.8, “Arbiter Event
- Page 295 and 296:
Chapter 8 e300 Processor Core Overv
- Page 297 and 298:
e300 Processor Core Overview The e3
- Page 299 and 300:
e300 Processor Core Overview • In
- Page 301 and 302:
e300 Processor Core Overview For a
- Page 303 and 304:
8.1.5 Memory Subsystem Support e300
- Page 305 and 306:
e300 Processor Core Overview Typica
- Page 307 and 308:
e300 Processor Core Overview • Th
- Page 309 and 310:
e300 Processor Core Overview regist
- Page 311 and 312:
e300 Processor Core Overview The fo
- Page 313 and 314:
e300 Processor Core Overview 16 EE
- Page 315 and 316:
e300 Processor Core Overview • Th
- Page 317 and 318:
e300 Processor Core Overview 11 DPM
- Page 319 and 320:
Table 8-5 shows the bit definitions
- Page 321 and 322:
8.4.2.1 Power Architecture Instruct
- Page 323 and 324:
8.4.3 Cache Implementation e300 Pro
- Page 325 and 326:
e300 Processor Core Overview Cache
- Page 327 and 328:
e300 Processor Core Overview the e3
- Page 329 and 330:
Interrupt Type Data store translati
- Page 331 and 332:
e300 Processor Core Overview an int
- Page 333 and 334:
e300 Processor Core Overview These
- Page 335 and 336:
e300 Processor Core Overview Data c
- Page 337 and 338:
Chapter 9 Integrated Programmable I
- Page 339 and 340:
QUICC Engine USB 2.0 I2C DUART SPI
- Page 341 and 342:
Integrated Programmable Interrupt C
- Page 343 and 344:
Integrated Programmable Interrupt C
- Page 345 and 346:
Integrated Programmable Interrupt C
- Page 347 and 348:
Table 9-7 shows the definition of I
- Page 349 and 350:
Table 9-9 defines the bit fields of
- Page 351 and 352:
Integrated Programmable Interrupt C
- Page 353 and 354:
Table 9-14 defines the bit fields o
- Page 355 and 356:
Table 9-16 defines the bit fields o
- Page 357 and 358:
Integrated Programmable Interrupt C
- Page 359 and 360:
16-27 MIXA4P- MIXA7P Same as MIXA0P
- Page 361 and 362:
Integrated Programmable Interrupt C
- Page 363 and 364:
Table 9-25 defines the bit fields o
- Page 365 and 366:
Table 9-28 defines the bit fields o
- Page 367 and 368:
9.5.20 System External Interrupt Fo
- Page 369 and 370:
Integrated Programmable Interrupt C
- Page 371 and 372:
Table 9-36 defines the bit fields o
- Page 373 and 374:
Integrated Programmable Interrupt C
- Page 375 and 376:
Integrated Programmable Interrupt C
- Page 377 and 378:
Table 9-38. Interrupt Source Priori
- Page 379 and 380:
Table 9-38. Interrupt Source Priori
- Page 381 and 382:
Integrated Programmable Interrupt C
- Page 383 and 384:
Chapter 10 DDR Memory Controller 10
- Page 385 and 386:
DDR Memory Controller • Automatic
- Page 387 and 388:
10.3.2 Detailed Signal Descriptions
- Page 389 and 390:
MCS[0:1] O Chip selects. Two chip s
- Page 391 and 392:
10.4.1 Register Descriptions DDR Me
- Page 393 and 394:
8 AP_n_EN Chip select n auto-precha
- Page 395 and 396:
Table 10-9 describes TIMING_CFG_0 f
- Page 397 and 398:
DDR Memory Controller 1-3 PRETOACT
- Page 399 and 400:
Table 10-11 describes the TIMING_CF
- Page 401 and 402:
Table 10-12 describes the DDR_SDRAM
- Page 403 and 404:
Table 10-13 describes the DDR_SDRAM
- Page 405 and 406:
Table 10-15 describes the DDR_SDRAM
- Page 407 and 408:
Table 10-16. DDR_SDRAM_MD_CNTL Fiel
- Page 409 and 410:
Table 10-20 describes the DDR_SDRAM
- Page 411 and 412:
DDR Memory Controller Programmable
- Page 413 and 414:
DDR Memory Controller buffering req
- Page 415 and 416:
DDR Memory Controller If a transact
- Page 417 and 418:
DDR Memory Controller • Write Lat
- Page 419 and 420:
Table 10-29. DDR SDRAM Interface Ti
- Page 421 and 422:
SDRAM Clock MCS0 MRAS MCAS MAn MWE
- Page 423 and 424:
Figure 10-28 shows the use of the W
- Page 425 and 426:
Table 10-30 summarizes the refresh
- Page 427 and 428:
DDR Memory Controller is desired wi
- Page 429 and 430:
DDR Memory Controller Table 10-32.
- Page 431 and 432:
Chapter 11 Enhanced Local Bus Contr
- Page 433 and 434:
Enhanced Local Bus Controller — G
- Page 435 and 436:
Name LGPL3/ LFWP LGTA/ LFRB/ LGPL4/
- Page 437 and 438:
Enhanced Local Bus Controller Table
- Page 439 and 440:
Enhanced Local Bus Controller 0x0A4
- Page 441 and 442:
24-26 MSEL Machine select. Specifie
- Page 443 and 444:
11.3.1.2.2 Option Registers (ORn)
- Page 445 and 446:
11.3.1.2.3 Option Registers (ORn)
- Page 447 and 448:
Table 11-8. ORn—FCM Field Descrip
- Page 449 and 450:
20-22 — Reserved 11.3.1.3 UPM Mem
- Page 451 and 452:
Table 11-11. MxMR Field Description
- Page 453 and 454:
Enhanced Local Bus Controller an ex
- Page 455 and 456:
Table 11-15 describes LURT fields.
- Page 457 and 458:
11.3.1.10 Transfer Error Check Disa
- Page 459 and 460:
11.3.1.12 Transfer Error Attributes
- Page 461 and 462:
Table 11-21 describes LBCR fields.
- Page 463 and 464:
11.3.1.16 Flash Mode Register (FMR)
- Page 465 and 466:
Table 11-24 describes FIR fields. 1
- Page 467 and 468:
Enhanced Local Bus Controller Offse
- Page 469 and 470:
Enhanced Local Bus Controller FCM p
- Page 471 and 472:
Enhanced Local Bus Controller In ge
- Page 473 and 474:
NOTE When the FCM is in the middle
- Page 475 and 476:
Enhanced Local Bus Controller Table
- Page 477 and 478:
Table 11-31. GPCM Write Control Sig
- Page 479 and 480:
Enhanced Local Bus Controller case
- Page 481 and 482:
Enhanced Local Bus Controller When
- Page 483 and 484:
LCLK LAD LALE LCSn LBCTL Rd. Addres
- Page 485 and 486:
Enhanced Local Bus Controller first
- Page 487 and 488:
Enhanced Local Bus Controller Basic
- Page 489 and 490:
Enhanced Local Bus Controller small
- Page 491 and 492:
Enhanced Local Bus Controller adjac
- Page 493 and 494:
11.4.3.2.2 FCM No-Operation Instruc
- Page 495 and 496:
11.4.3.3.2 FCM Command, Address, an
- Page 497 and 498:
Enhanced Local Bus Controller remai
- Page 499 and 500:
Enhanced Local Bus Controller When
- Page 501 and 502:
Enhanced Local Bus Controller 6. Th
- Page 503 and 504:
11.4.4.1.1 Memory Access Requests T
- Page 505 and 506:
In order to enforce proper ordering
- Page 507 and 508:
LCLK T1 T2 T3 T4 LCLK T1 T2 T3 T4 1
- Page 509 and 510:
Table 11-38. RAM Word Field Descrip
- Page 511 and 512:
Table 11-38. RAM Word Field Descrip
- Page 513 and 514:
Enhanced Local Bus Controller Conti
- Page 515 and 516:
11.4.4.4.8 Data Valid and Data Samp
- Page 517 and 518:
11.5 Initialization/Application Inf
- Page 519 and 520:
Enhanced Local Bus Controller For d
- Page 521 and 522:
Table 11-41 lists the bytes require
- Page 523 and 524:
Enhanced Local Bus Controller concl
- Page 525 and 526:
Enhanced Local Bus Controller happe
- Page 527 and 528:
LCLK LAD LALE LCSn (RAS) LGPL1 (R/W
- Page 529 and 530:
LCLK LAD LALE A TA LA LCSn (RAS) LB
- Page 531 and 532:
Enhanced Local Bus Controller mostl
- Page 533 and 534:
Chapter 12 Enhanced Secure Digital
- Page 535 and 536:
Figure 12-2 is a block diagram of t
- Page 537 and 538:
Table 12-1 shows the properties of
- Page 539 and 540:
12.4.1 DMA System Address Register
- Page 541 and 542:
Table 12-5 describes the CMDARG fie
- Page 543 and 544:
14-15 RSPTYP Response type select.
- Page 545 and 546:
Enhanced Secure Digital Host Contro
- Page 547 and 548:
Table 12-11 describes the PRSSTAT f
- Page 549 and 550:
Table 12-11. PRSSTAT Field Descript
- Page 551 and 552:
Table 12-12 describes the PROCTL fi
- Page 553 and 554:
Enhanced Secure Digital Host Contro
- Page 555 and 556:
Enhanced Secure Digital Host Contro
- Page 557 and 558:
Figure 12-12 shows the interrupt st
- Page 559 and 560:
Table 12-14. IRQSTAT Field Descript
- Page 561 and 562:
Enhanced Secure Digital Host Contro
- Page 563 and 564:
12.4.12 Interrupt Signal Enable Reg
- Page 565 and 566:
12.4.13 Auto CMD12 Error Status Reg
- Page 567 and 568:
12.4.14 Host Controller Capabilitie
- Page 569 and 570:
Figure 12-18 shows the force event
- Page 571 and 572:
12.5.1 Data Buffer Enhanced Secure
- Page 573 and 574:
Enhanced Secure Digital Host Contro
- Page 575 and 576:
• Detects bus state on SD_DAT[0]
- Page 577 and 578:
12.5.6.1 Interrupts in 1-bit Mode E
- Page 579 and 580:
Enhanced Secure Digital Host Contro
- Page 581 and 582:
Enhanced Secure Digital Host Contro
- Page 583 and 584:
12.6.2.4 Card Registry Card registr
- Page 585 and 586:
Enhanced Secure Digital Host Contro
- Page 587 and 588:
Enhanced Secure Digital Host Contro
- Page 589 and 590:
Enhanced Secure Digital Host Contro
- Page 591 and 592:
12.6.4.3 Query, Enable and Disable
- Page 593 and 594:
CMD INDEX CMD7 ac [31-16] RCA [15-0
- Page 595 and 596:
CMD INDEX Enhanced Secure Digital H
- Page 597 and 598:
12.7 Software Restrictions This sec
- Page 599 and 600:
Chapter 13 DMA Engine 1 The direct
- Page 601 and 602:
MPC8306 PowerQUICC II Pro Integrate
- Page 603 and 604:
Table 13-2 describes the DMACR fiel
- Page 605 and 606:
MPC8306 PowerQUICC II Pro Integrate
- Page 607 and 608:
Figure 13-4 shows the DMA enable re
- Page 609 and 610:
Table 13-6 defines the DMASERQ fiel
- Page 611 and 612:
Table 13-9 defines the DMACEEI fiel
- Page 613 and 614:
Table 13-12 defines DMASSRT fields.
- Page 615 and 616:
MPC8306 PowerQUICC II Pro Integrate
- Page 617 and 618:
MPC8306 PowerQUICC II Pro Integrate
- Page 619 and 620:
Figure 13-19 shows the TCD word 1 f
- Page 621 and 622:
Figure 13-22 shows the TCD word 4 f
- Page 623 and 624:
Table 13-25 describes the TCD word
- Page 625 and 626:
Table 13-26. TCD Word 7 (TCD.{biter
- Page 627 and 628:
MPC8306 PowerQUICC II Pro Integrate
- Page 629 and 630:
descriptor. The updates to the TCD
- Page 631 and 632:
MPC8306 PowerQUICC II Pro Integrate
- Page 633 and 634:
13.7 TCD Status MPC8306 PowerQUICC
- Page 635 and 636:
13.9.2 Dynamic channel linking and
- Page 637 and 638:
Chapter 14 DMA Engine 2 The DMA Eng
- Page 639 and 640:
MPC8306 PowerQUICC II Pro Integrate
- Page 641 and 642:
14.3.1.2 DMA Status Register (DMASR
- Page 643 and 644:
14.3.1.4 DMA Source Address Registe
- Page 645 and 646:
2-1 — Reserved 14.3.1.8 DMA Gener
- Page 647 and 648:
Table 14-9. DMA Segment Descriptor
- Page 649 and 650:
14.5.2 Initialization Steps in Chai
- Page 651 and 652:
Chapter 15 FlexCAN 15.1 Introductio
- Page 653 and 654:
are stored in an embedded RAM dedic
- Page 655 and 656:
MPC8306 PowerQUICC II Pro Integrate
- Page 657 and 658:
Table 15-3 shows a standard/extende
- Page 659 and 660:
The encoding of CODE field is shown
- Page 661 and 662:
Figure 15-4 shows ID table structur
- Page 663 and 664:
Table 15-8. Module Configuration Re
- Page 665 and 666:
MPC8306 PowerQUICC II Pro Integrate
- Page 667 and 668:
MPC8306 PowerQUICC II Pro Integrate
- Page 669 and 670:
Table 15-10. Free Running Timer (TI
- Page 671 and 672:
• Transmit Error Counter (Tx_Err_
- Page 673 and 674:
Table 15-13. Error and Status Regis
- Page 675 and 676:
Table 15-14. Interrupt Masks 2 Regi
- Page 677 and 678:
Figure 15-16 shows the interrupt fl
- Page 679 and 680:
MPC8306 PowerQUICC II Pro Integrate
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MPC8306 PowerQUICC II Pro Integrate
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MPC8306 PowerQUICC II Pro Integrate
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MPC8306 PowerQUICC II Pro Integrate
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MPC8306 PowerQUICC II Pro Integrate
- Page 689 and 690:
Table 15-19. Time Segment Syntax Tr
- Page 691 and 692:
MPC8306 PowerQUICC II Pro Integrate
- Page 693 and 694:
MPC8306 PowerQUICC II Pro Integrate
- Page 695 and 696:
Chapter 16 Universal Serial Bus Int
- Page 697 and 698:
16.2 External Signals Universal Ser
- Page 699 and 700:
Table 16-3. USB Interface Memory Ma
- Page 701 and 702:
Table 16-4 provides bit description
- Page 703 and 704:
Table 16-7. HCCPARAMS Register Fiel
- Page 705 and 706:
Table 16-10 provides bit descriptio
- Page 707 and 708:
16.3.2.2 USB Status Register (USBST
- Page 709 and 710:
1 UEI (USBERRINT) 0 UI (USBINT) 16.
- Page 711 and 712:
Universal Serial Bus Interface this
- Page 713 and 714:
Figure 16-12 shows the device addre
- Page 715 and 716:
Table 16-19 describes the master in
- Page 717 and 718:
ULPI VIEWPORT is shown in Figure 16
- Page 719 and 720:
Universal Serial Bus Interface forc
- Page 721 and 722:
Universal Serial Bus Interface 12 P
- Page 723 and 724:
16.3.2.15 On-The-Go Status and Cont
- Page 725 and 726:
Universal Serial Bus Interface 19 B
- Page 727 and 728:
Universal Serial Bus Interface 16.3
- Page 729 and 730:
15-3 — Reserved, should be cleare
- Page 731 and 732:
17 — Reserved, should be cleared.
- Page 733 and 734:
Table 16-32. ENDPTCTRLn Register Fi
- Page 735 and 736:
Universal Serial Bus Interface The
- Page 737 and 738:
28-30 — Reserved, should be clear
- Page 739 and 740:
Universal Serial Bus Interface devi
- Page 741 and 742:
Universal Serial Bus Interface Fram
- Page 743 and 744:
16.5.3.1 Next Link Pointer Universa
- Page 745 and 746:
Table 16-42-Table 16-45 describe bu
- Page 747 and 748:
Table 16-47 describes the endpoint
- Page 749 and 750:
16.5.4.4 siTD Buffer Pointer List (
- Page 751 and 752:
16.5.5.1 Next qTD Pointer Universal
- Page 753 and 754:
Table 16-55. qTD Token (DWord 2) (c
- Page 755 and 756:
16.5.5.4 qTD Buffer Page Pointer Li
- Page 757 and 758:
Universal Serial Bus Interface 2-1
- Page 759 and 760:
Universal Serial Bus Interface 15-8
- Page 761 and 762:
16.5.7.1 FTSN Normal Path Pointer U
- Page 763 and 764:
Universal Serial Bus Interface sche
- Page 765 and 766:
Universal Serial Bus Interface PORT
- Page 767 and 768:
Universal Serial Bus Interface The
- Page 769 and 770:
Universal Serial Bus Interface Soft
- Page 771 and 772:
16.6.8.1 Host Controller Operationa
- Page 773 and 774:
Universal Serial Bus Interface Figu
- Page 775 and 776:
Universal Serial Bus Interface stat
- Page 777 and 778:
Universal Serial Bus Interface -- p
- Page 779 and 780:
Figure 16-50 shows an example illus
- Page 781 and 782:
Figure 16-51 illustrates these requ
- Page 783 and 784:
16.6.11 Ping Control Universal Seri
- Page 785 and 786:
16.6.12.1.1 Asynchronous—Do-Start
- Page 787 and 788:
Universal Serial Bus Interface and
- Page 789 and 790:
Universal Serial Bus Interface •
- Page 791 and 792:
Universal Serial Bus Interface Poin
- Page 793 and 794:
Universal Serial Bus Interface corr
- Page 795 and 796:
Universal Serial Bus Interface -- t
- Page 797 and 798:
Universal Serial Bus Interface The
- Page 799 and 800:
Universal Serial Bus Interface a si
- Page 801 and 802:
Universal Serial Bus Interface tran
- Page 803 and 804:
Universal Serial Bus Interface •
- Page 805 and 806:
Universal Serial Bus Interface tran
- Page 807 and 808:
Universal Serial Bus Interface •
- Page 809 and 810:
Universal Serial Bus Interface The
- Page 811 and 812:
Universal Serial Bus Interface is m
- Page 813 and 814:
Universal Serial Bus Interface 4. S
- Page 815 and 816:
Universal Serial Bus Interface endp
- Page 817 and 818:
16.6.14.2.4 Host System Error Unive
- Page 819 and 820:
Figure 16-61 shows the Endpoint Que
- Page 821 and 822:
Table 16-77 describes the multiple
- Page 823 and 824:
16.8 Device Operational Model Table
- Page 825 and 826:
Power Interruption When the Host Re
- Page 827 and 828:
16.8.2.2 Suspend/Resume This sectio
- Page 829 and 830:
Universal Serial Bus Interface The
- Page 831 and 832:
Universal Serial Bus Interface Note
- Page 833 and 834:
16.8.3.5 Control Endpoint Operation
- Page 835 and 836:
Token Type Table 16-89. Control End
- Page 837 and 838:
Universal Serial Bus Interface must
- Page 839 and 840:
NOTE After the acknowledge has occu
- Page 841 and 842:
Universal Serial Bus Interface Comp
- Page 843 and 844:
Execution Order 1b USB Interrupt EN
- Page 845 and 846:
Universal Serial Bus Interface low-
- Page 847 and 848:
16.9.1.5.3 Asynchronous Transaction
- Page 849 and 850:
Universal Serial Bus Interface •
- Page 851 and 852:
Figure 16-69 shows ULPI data transm
- Page 853 and 854:
Chapter 17 I 2 C Interfaces This ch
- Page 855 and 856:
sequence mode according to the BOOT
- Page 857 and 858:
MPC8306 PowerQUICC II Pro Integrate
- Page 859 and 860:
17.3.1.3 I 2 Cn Control Register (I
- Page 861 and 862:
17.3.1.5 I 2 Cn Data Register (I2Cn
- Page 863 and 864:
MPC8306 PowerQUICC II Pro Integrate
- Page 865 and 866:
MPC8306 PowerQUICC II Pro Integrate
- Page 867 and 868:
17.4.3 Handshaking MPC8306 PowerQUI
- Page 869 and 870:
MPC8306 PowerQUICC II Pro Integrate
- Page 871 and 872:
MPC8306 PowerQUICC II Pro Integrate
- Page 873 and 874:
Master Xmit Generate STOP Write nex
- Page 875 and 876:
MPC8306 PowerQUICC II Pro Integrate
- Page 877 and 878:
Chapter 18 DUART This chapter descr
- Page 879 and 880:
18.1.2 Modes of Operation The commu
- Page 881 and 882:
information about each register. Un
- Page 883 and 884:
Table 18-5 describes the UTHR. 18.3
- Page 885 and 886:
Table 18-9 describes the UIER field
- Page 887 and 888:
Figure 18-8 shows the bits in the U
- Page 889 and 890:
Table 18-14 describes the ULCR fiel
- Page 891 and 892:
18.3.1.10 Line Status Registers (UL
- Page 893 and 894:
18.3.1.12 Scratch Registers (USCR1
- Page 895 and 896:
MPC8306 PowerQUICC II Pro Integrate
- Page 897 and 898:
18.4.3 Local Loopback Mode MPC8306
- Page 899 and 900:
18.5 DUART Initialization/Applicati
- Page 901 and 902:
Chapter 19 Serial Peripheral Interf
- Page 903 and 904:
19.2.2 SPI Transmission and Recepti
- Page 905 and 906:
Serial Peripheral Interface Transmi
- Page 907 and 908:
19.3.1 Overview Table 19-1 lists si
- Page 909 and 910:
19.4.1 Register Descriptions This s
- Page 911 and 912:
Serial Peripheral Interface Figure
- Page 913 and 914:
Serial Peripheral Interface SPIM bi
- Page 915 and 916:
19.4.1.6 SPI Receive Data Hold Regi
- Page 917 and 918:
Chapter 20 JTAG/Testing Support 20.
- Page 919 and 920:
TDO O JTAG test data output. JTAG/T
- Page 921 and 922:
Chapter 21 General Purpose I/O (GPI
- Page 923 and 924:
General Purpose I/O (GPIO) 0xD00 GP
- Page 925 and 926:
21.3.4 GPIOn Interrupt Event Regist
- Page 927 and 928:
Chapter 22 QUICC Engine Block on th
- Page 929 and 930:
QUICC Engine Block on the MPC8306 a
- Page 931 and 932:
QUICC Engine Block on the MPC8306 a
- Page 933 and 934:
22.2.1.5 System Interface—Arbitra
- Page 935 and 936:
6 BER_1_MSK Mask bus error events.
- Page 937 and 938:
Figure 22-7. DMA Command Queue QUIC
- Page 939 and 940:
Table 22-6 describes the SDTAx fiel
- Page 941 and 942:
QUICC Engine Block on the MPC8306 a
- Page 943 and 944:
Table 22-9. Interrupt Source Priori
- Page 945 and 946:
QUICC Engine Block on the MPC8306 a
- Page 947 and 948:
22.2.1.7.6 Interrupt Vector Generat
- Page 949 and 950:
QUICC Engine Block on the MPC8306 a
- Page 951 and 952:
QUICC Engine Block on the MPC8306 a
- Page 953 and 954:
Table 22-14 defines the bit fields
- Page 955 and 956:
Table 22-16 describes CIPXCC fields
- Page 957 and 958:
22.2.1.8.8 QUICC Engine System Inte
- Page 959 and 960:
QUICC Engine Block on the MPC8306 a
- Page 961 and 962:
22.2.1.8.13 QUICC Engine RISC Inter
- Page 963 and 964:
22.2.2 Configuration - Parameter RA
- Page 965 and 966:
22.2.2.5 QUICC Engine Microcode Rev
- Page 967 and 968:
Table 22-25 shows the CEVTxxMR fiel
- Page 969 and 970:
QUICC Engine Block on the MPC8306 a
- Page 971 and 972:
22.2.3.2 QUICC Engine Multiplexing
- Page 973 and 974:
Appendix A Complete List of Configu
- Page 975 and 976:
A.3 Watchdog Timer (WDT) A.4 Real T
- Page 977 and 978:
Complete List of Configuration, Con
- Page 979 and 980:
A.10 Reset Configuration A.11 Clock
- Page 981 and 982:
Complete List of Configuration, Con
- Page 983 and 984:
Table A-16. DUART Registers (contin
- Page 985 and 986:
A.18 Serial Peripheral Interface (S
- Page 987 and 988:
Complete List of Configuration, Con
- Page 989 and 990:
0x180- 0x27F 0x280- 0x047F 0x480- 0
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