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Tables Table Number Title MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual, Rev. 0 Page Number A-11 Clock Configuration Registers................................................................................................ 1-7 A-12 Power Management Controller (PMC) Registers ................................................................... 1-7 A-13 General Purpose I/O (GPIO) Registers................................................................................... 1-8 A-14 DDR Memory Controller Registers ........................................................................................ 1-8 A-15 I 2 C Controller Registers..........................................................................................................1-9 A-16 DUART Registers ................................................................................................................. 1-10 A-17 Enhanced Local Bus Controller Registers ............................................................................ 1-11 A-18 Serial Peripheral Interface (SPI) Registers ........................................................................... 1-13 A-19 DMA Engine 1 ...................................................................................................................... 1-13 A-20 Module Memory Map ...........................................................................................................1-14 A-21 Enhanced Secure Digital Host Controller (eSDHC) Registers............................................. 1-15 A-22 FlexCAN Memory Map ........................................................................................................ 1-16 A-23 USB Interface Registers........................................................................................................ 1-17 xlvi Freescale Semiconductor
About This Book This reference manual defines the functionality of the MPC8306 and MPC8306S. The device is a cost-effective, low-power, highly integrated host processor that addresses the requirements of networking applications such as low-end printing, smart grid home energy gateway, data concentrators, wireless LAN access points, wireless femto base stations, and industrial applications, such as industrial control and factory automation. The MPC8306 and MPC8306S extend the PowerQUICC II Pro family, adding high CPU performance, additional functionality, and faster interfaces while addressing the requirements related to time-to-market, price, power consumption, and package size. Audience It is assumed that the reader understands operating systems, microprocessor system design, and the basic principles of RISC processing. Organization Following is a summary and a brief description of the major parts of this reference manual: • Chapter 1, “Overview,” provides a high-level description of features and functionality of the MPC8306 and MPC8306S. It describes the device, its interfaces, and the programming model. The functional operation of the device, with emphasis on peripheral functions, is also described. • Chapter 2, “Memory Map,” describes the memory map of the device. An overview of the local address map is provided. Next, a complete listing of all memory-mapped registers is provided, with cross references to the sections detailing descriptions of each. • Chapter 3, “Signal Descriptions,” provides a listing of all the external signals, cross-references for signals that serve multiple functions, their functional blocks, and I/O states. Also, these signals are listed by alphabetical order. • Chapter 4, “Reset, Clocking, and Initialization,” describes the hard and soft resets, the power-on reset (POR) sequence, power-on reset configuration, clocking, and initialization of the device. • Chapter 5, “System boot,” describes the overall initialization of the MPC8306. • Chapter 6, “System Configuration,” provides an overview of several functions that control the local access windows, system configuration, software watchdog, real time clock, periodic and general purpose timers, power management, protection, and general utilities. • Chapter 7, “Arbiter and Bus Monitor,” provides an overview of the arbiter in the device. Also, it describes the configuration, control, and status registers of the arbiter. • Chapter 8, “e300 Processor Core Overview,” provides an overview of the basic functionality of the processor core and briefly describes how the functional units interact. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual, Rev. 0 Freescale Semiconductor xlvii
Page 1 and 2: MPC8306 PowerQUICC II Pro Integrate
Page 3 and 4: Contents Paragraph Number Title Abo
Page 5 and 6: Contents Paragraph Number Title MPC
Page 11 and 12: Contents Paragraph Number Title Cha
Page 13 and 14: Contents Paragraph Number Title Cha
Page 19 and 20: Figures Figure Number Title MPC8306
Page 33 and 34: Tables Table Number Title MPC8306 P
Page 45: Tables Table Number Title MPC8306 P
Page 49 and 50: • Chapter 20, “JTAG/Testing Sup
Page 51 and 52: Acronyms and Abbreviations Table i
Page 53 and 54: RISC Reduced instruction set comput
Page 55 and 56: Chapter 1 Overview This chapter pro
Page 65 and 66: 1.3.2 QUICC Engine Block MPC8306 Po
Page 67 and 68: • Some of the interfaces are mult
Page 69 and 70: 1.3.2.6 QUICC Engine UCC Capabiliti
Page 73 and 74: • Interrupt • Isochronous 1.3.7
Page 75 and 76: 1.3.10 DMA Engine 1 MPC8306 PowerQU
Page 77 and 78: Chapter 2 Memory Map This chapter d
Page 79 and 80: 0x0_4B00-0x0_4FFF Reserved — 1.25
Page 81 and 82: Chapter 3 Signal Descriptions This
Page 83 and 84: DDR2 Memory Interface 48 Signals eL
Page 87 and 88: UART1_SOUT[1] DUART serial data out
Page 89 and 90: Table 3-1. MPC8306 Signal Reference
Page 95 and 96: HDLC2_TXCLK HDLC2 transmit clock HD
Page 97 and 98:
MPC8306 PowerQUICC II Pro Integrate
Page 99 and 100:
Table 3-2 lists the signals in alph
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Name Description FEC3_RX_DV FEC3 re
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Name Description GPIO[37] General p
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Name Description HDLC1_RTS HDLC1 re
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Name Description MPC8306 PowerQUICC
Page 109 and 110:
Name Description SD_CD Card detecti
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Name Description Table 3-2. MPC8306
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DDR2 Memory Interface 48 Signals eL
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Table 3-3. MPC8306S Signal Referenc
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QE_EXT_REQ_3 QUICC Engine external
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Page 129 and 130:
Name Description Table 3-4. MPC8306
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Page 133 and 134:
Page 135 and 136:
Name Description LCS[6] LBC chip se
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Name Description QE_EXT_REQ_4 QUICC
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Name Description UART1_SOUT[1] DUAR
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Table 3-5. Output Signal States Dur
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Chapter 4 Reset, Clocking, and Init
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FEC1_TX_CLK, FEC2_TX_CLK, FEC3_TX_C
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Table 4-4 identifies the reset acti
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Figure 4-1 shows a timing diagram o
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Reset, Clocking, and Initialization
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4.3.2.1 Reset Configuration Word Lo
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4.3.2.1.2 System PLL Configuration
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4.5.1.3 Reset Status Register (RSR)
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4.5.1.5 Reset Protection Register (
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4.5.2.3 System Clock Control Regist
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Chapter 5 System boot This chapter
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0x5C-0x5F Reserved 0x60-0x63 Execut
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Page 185 and 186:
Page 187 and 188:
Page 189 and 190:
0x68-0x6B N. Number of Config Addre
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Figure 5-6 shows the external signa
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Chapter 6 System Configuration 6.1
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System Configuration In this exampl
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6.2.4 Local Access Register Descrip
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NOTE ALTCBAR is not considered a lo
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6.2.4.4.1 LBLAWAR0[EN] and LBLAWAR0
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6.2.4.6.1 DDRLAWAR0[EN] and DDRLAWA
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Local Memory Offset (Hex) System Co
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Table 6-19 defines the bit fields o
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Figure 6-12 shows SICR_1. System Co
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Table 6-23. SICR_1 Bit Settings for
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System Configuration Table 6-25 def
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6.3.2.9 6.3.2.10 Debug Configuratio
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Table 6-27. SIDCR0 Bit Settings (co
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12-14 USB_DELAY_C USBDR_STP 000 15-
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6.3.2.14 eSDHC Control Register (SD
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System Configuration The CAN access
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2 PULLUP_ CTRL_2 3 PULLUP_ CTRL_3 4
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System Configuration The CAN interr
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6.3.2.18 DUART Interrupt Status Reg
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System Configuration — LCLK1 and
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6.4.4 WDT Memory Map/Register Defin
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System Configuration Although most
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System Configuration register (RTCT
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6.5.5.5 Real Time Counter Event Reg
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System Configuration — RTC enable
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Table 6-50 describes the external P
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6.6.5.3 Periodic Interval Timer Pre
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Figure 6-44shows the functional PIT
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System Configuration • Two timers
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System Configuration TGATE1 TGATE1
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System Configuration 0x020 Timer 3
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The GTCFR2 register is shown in Fig
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System Configuration GTCNRn[CNV] fi
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6.7.6 Functional Description System
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System Configuration • Pair-casca
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6.8.1 External Signal Description T
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System Mode Low Power (PMCCR[SLPEN]
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Chapter 7 Arbiter and Bus Monitor T
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7.2.1 Arbiter Configuration Registe
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Table 7-3 describes ATR fields. 7.2
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29 AO Address only transfer type. T
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11-15 MSTR_ID Master Id. 00000 e300
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7.3 Functional Description The foll
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Z Y X Level 3 Figure 7-10. An Examp
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Arbiter and Bus Monitor 3. Issues r
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• Section 7.2.8, “Arbiter Event
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Chapter 8 e300 Processor Core Overv
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e300 Processor Core Overview The e3
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e300 Processor Core Overview • In
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e300 Processor Core Overview For a
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8.1.5 Memory Subsystem Support e300
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e300 Processor Core Overview Typica
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e300 Processor Core Overview • Th
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e300 Processor Core Overview regist
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e300 Processor Core Overview The fo
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e300 Processor Core Overview 16 EE
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e300 Processor Core Overview • Th
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e300 Processor Core Overview 11 DPM
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Table 8-5 shows the bit definitions
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8.4.2.1 Power Architecture Instruct
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8.4.3 Cache Implementation e300 Pro
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e300 Processor Core Overview Cache
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e300 Processor Core Overview the e3
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Interrupt Type Data store translati
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e300 Processor Core Overview an int
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e300 Processor Core Overview These
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e300 Processor Core Overview Data c
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Chapter 9 Integrated Programmable I
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QUICC Engine USB 2.0 I2C DUART SPI
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Integrated Programmable Interrupt C
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Page 345 and 346:
Page 347 and 348:
Table 9-7 shows the definition of I
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Table 9-9 defines the bit fields of
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Page 353 and 354:
Page 355 and 356:
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16-27 MIXA4P- MIXA7P Same as MIXA0P
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Page 363 and 364:
Page 365 and 366:
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9.5.20 System External Interrupt Fo
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Table 9-38. Interrupt Source Priori
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Page 381 and 382:
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Chapter 10 DDR Memory Controller 10
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DDR Memory Controller • Automatic
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10.3.2 Detailed Signal Descriptions
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MCS[0:1] O Chip selects. Two chip s
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10.4.1 Register Descriptions DDR Me
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8 AP_n_EN Chip select n auto-precha
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Table 10-9 describes TIMING_CFG_0 f
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DDR Memory Controller 1-3 PRETOACT
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Table 10-11 describes the TIMING_CF
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Table 10-12 describes the DDR_SDRAM
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Page 405 and 406:
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Table 10-16. DDR_SDRAM_MD_CNTL Fiel
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Page 411 and 412:
DDR Memory Controller Programmable
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DDR Memory Controller buffering req
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DDR Memory Controller If a transact
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DDR Memory Controller • Write Lat
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Table 10-29. DDR SDRAM Interface Ti
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SDRAM Clock MCS0 MRAS MCAS MAn MWE
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Figure 10-28 shows the use of the W
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Table 10-30 summarizes the refresh
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DDR Memory Controller is desired wi
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DDR Memory Controller Table 10-32.
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Chapter 11 Enhanced Local Bus Contr
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Enhanced Local Bus Controller — G
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Name LGPL3/ LFWP LGTA/ LFRB/ LGPL4/
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Enhanced Local Bus Controller Table
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Enhanced Local Bus Controller 0x0A4
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24-26 MSEL Machine select. Specifie
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11.3.1.2.2 Option Registers (ORn)
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11.3.1.2.3 Option Registers (ORn)
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Table 11-8. ORn—FCM Field Descrip
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20-22 — Reserved 11.3.1.3 UPM Mem
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Table 11-11. MxMR Field Description
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Enhanced Local Bus Controller an ex
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Table 11-15 describes LURT fields.
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11.3.1.10 Transfer Error Check Disa
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11.3.1.12 Transfer Error Attributes
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Table 11-21 describes LBCR fields.
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11.3.1.16 Flash Mode Register (FMR)
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Table 11-24 describes FIR fields. 1
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Enhanced Local Bus Controller Offse
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Enhanced Local Bus Controller FCM p
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Enhanced Local Bus Controller In ge
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NOTE When the FCM is in the middle
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Enhanced Local Bus Controller Table
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Table 11-31. GPCM Write Control Sig
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Enhanced Local Bus Controller case
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Enhanced Local Bus Controller When
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LCLK LAD LALE LCSn LBCTL Rd. Addres
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Enhanced Local Bus Controller first
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Enhanced Local Bus Controller Basic
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Enhanced Local Bus Controller small
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Enhanced Local Bus Controller adjac
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11.4.3.2.2 FCM No-Operation Instruc
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11.4.3.3.2 FCM Command, Address, an
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Enhanced Local Bus Controller remai
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Enhanced Local Bus Controller When
Page 501 and 502:
Enhanced Local Bus Controller 6. Th
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11.4.4.1.1 Memory Access Requests T
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In order to enforce proper ordering
Page 507 and 508:
LCLK T1 T2 T3 T4 LCLK T1 T2 T3 T4 1
Page 509 and 510:
Table 11-38. RAM Word Field Descrip
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Table 11-38. RAM Word Field Descrip
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Enhanced Local Bus Controller Conti
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11.4.4.4.8 Data Valid and Data Samp
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11.5 Initialization/Application Inf
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Enhanced Local Bus Controller For d
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Table 11-41 lists the bytes require
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Enhanced Local Bus Controller concl
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Enhanced Local Bus Controller happe
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LCLK LAD LALE LCSn (RAS) LGPL1 (R/W
Page 529 and 530:
LCLK LAD LALE A TA LA LCSn (RAS) LB
Page 531 and 532:
Enhanced Local Bus Controller mostl
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Chapter 12 Enhanced Secure Digital
Page 535 and 536:
Figure 12-2 is a block diagram of t
Page 537 and 538:
Table 12-1 shows the properties of
Page 539 and 540:
12.4.1 DMA System Address Register
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Table 12-5 describes the CMDARG fie
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14-15 RSPTYP Response type select.
Page 545 and 546:
Enhanced Secure Digital Host Contro
Page 547 and 548:
Table 12-11 describes the PRSSTAT f
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Table 12-11. PRSSTAT Field Descript
Page 551 and 552:
Table 12-12 describes the PROCTL fi
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Page 555 and 556:
Page 557 and 558:
Figure 12-12 shows the interrupt st
Page 559 and 560:
Table 12-14. IRQSTAT Field Descript
Page 561 and 562:
Page 563 and 564:
12.4.12 Interrupt Signal Enable Reg
Page 565 and 566:
12.4.13 Auto CMD12 Error Status Reg
Page 567 and 568:
12.4.14 Host Controller Capabilitie
Page 569 and 570:
Figure 12-18 shows the force event
Page 571 and 572:
12.5.1 Data Buffer Enhanced Secure
Page 573 and 574:
Page 575 and 576:
• Detects bus state on SD_DAT[0]
Page 577 and 578:
12.5.6.1 Interrupts in 1-bit Mode E
Page 579 and 580:
Page 581 and 582:
Page 583 and 584:
12.6.2.4 Card Registry Card registr
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Page 587 and 588:
Page 589 and 590:
Page 591 and 592:
12.6.4.3 Query, Enable and Disable
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CMD INDEX CMD7 ac [31-16] RCA [15-0
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CMD INDEX Enhanced Secure Digital H
Page 597 and 598:
12.7 Software Restrictions This sec
Page 599 and 600:
Chapter 13 DMA Engine 1 The direct
Page 601 and 602:
Page 603 and 604:
Table 13-2 describes the DMACR fiel
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Page 607 and 608:
Figure 13-4 shows the DMA enable re
Page 609 and 610:
Table 13-6 defines the DMASERQ fiel
Page 611 and 612:
Table 13-9 defines the DMACEEI fiel
Page 613 and 614:
Table 13-12 defines DMASSRT fields.
Page 615 and 616:
Page 617 and 618:
Page 619 and 620:
Figure 13-19 shows the TCD word 1 f
Page 621 and 622:
Figure 13-22 shows the TCD word 4 f
Page 623 and 624:
Table 13-25 describes the TCD word
Page 625 and 626:
Table 13-26. TCD Word 7 (TCD.{biter
Page 627 and 628:
Page 629 and 630:
descriptor. The updates to the TCD
Page 631 and 632:
Page 633 and 634:
13.7 TCD Status MPC8306 PowerQUICC
Page 635 and 636:
13.9.2 Dynamic channel linking and
Page 637 and 638:
Chapter 14 DMA Engine 2 The DMA Eng
Page 639 and 640:
Page 641 and 642:
14.3.1.2 DMA Status Register (DMASR
Page 643 and 644:
14.3.1.4 DMA Source Address Registe
Page 645 and 646:
2-1 — Reserved 14.3.1.8 DMA Gener
Page 647 and 648:
Table 14-9. DMA Segment Descriptor
Page 649 and 650:
14.5.2 Initialization Steps in Chai
Page 651 and 652:
Chapter 15 FlexCAN 15.1 Introductio
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are stored in an embedded RAM dedic
Page 655 and 656:
Page 657 and 658:
Table 15-3 shows a standard/extende
Page 659 and 660:
The encoding of CODE field is shown
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Figure 15-4 shows ID table structur
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Table 15-8. Module Configuration Re
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Page 667 and 668:
Page 669 and 670:
Table 15-10. Free Running Timer (TI
Page 671 and 672:
• Transmit Error Counter (Tx_Err_
Page 673 and 674:
Table 15-13. Error and Status Regis
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Table 15-14. Interrupt Masks 2 Regi
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Figure 15-16 shows the interrupt fl
Page 679 and 680:
Page 681 and 682:
Page 683 and 684:
Page 685 and 686:
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Table 15-19. Time Segment Syntax Tr
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Page 693 and 694:
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Chapter 16 Universal Serial Bus Int
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16.2 External Signals Universal Ser
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Table 16-3. USB Interface Memory Ma
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Table 16-4 provides bit description
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Table 16-7. HCCPARAMS Register Fiel
Page 705 and 706:
Table 16-10 provides bit descriptio
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16.3.2.2 USB Status Register (USBST
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1 UEI (USBERRINT) 0 UI (USBINT) 16.
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Universal Serial Bus Interface this
Page 713 and 714:
Figure 16-12 shows the device addre
Page 715 and 716:
Table 16-19 describes the master in
Page 717 and 718:
ULPI VIEWPORT is shown in Figure 16
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Universal Serial Bus Interface forc
Page 721 and 722:
Universal Serial Bus Interface 12 P
Page 723 and 724:
16.3.2.15 On-The-Go Status and Cont
Page 725 and 726:
Universal Serial Bus Interface 19 B
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Universal Serial Bus Interface 16.3
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15-3 — Reserved, should be cleare
Page 731 and 732:
17 — Reserved, should be cleared.
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Table 16-32. ENDPTCTRLn Register Fi
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Universal Serial Bus Interface The
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28-30 — Reserved, should be clear
Page 739 and 740:
Universal Serial Bus Interface devi
Page 741 and 742:
Universal Serial Bus Interface Fram
Page 743 and 744:
16.5.3.1 Next Link Pointer Universa
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Table 16-42-Table 16-45 describe bu
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Table 16-47 describes the endpoint
Page 749 and 750:
16.5.4.4 siTD Buffer Pointer List (
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16.5.5.1 Next qTD Pointer Universal
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Table 16-55. qTD Token (DWord 2) (c
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16.5.5.4 qTD Buffer Page Pointer Li
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Universal Serial Bus Interface 2-1
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Universal Serial Bus Interface 15-8
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16.5.7.1 FTSN Normal Path Pointer U
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Universal Serial Bus Interface sche
Page 765 and 766:
Universal Serial Bus Interface PORT
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Universal Serial Bus Interface Soft
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16.6.8.1 Host Controller Operationa
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Universal Serial Bus Interface Figu
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Universal Serial Bus Interface stat
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Universal Serial Bus Interface -- p
Page 779 and 780:
Figure 16-50 shows an example illus
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Figure 16-51 illustrates these requ
Page 783 and 784:
16.6.11 Ping Control Universal Seri
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16.6.12.1.1 Asynchronous—Do-Start
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Universal Serial Bus Interface and
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Universal Serial Bus Interface •
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Universal Serial Bus Interface Poin
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Universal Serial Bus Interface corr
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Universal Serial Bus Interface -- t
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Universal Serial Bus Interface a si
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Universal Serial Bus Interface tran
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Universal Serial Bus Interface tran
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Universal Serial Bus Interface is m
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Universal Serial Bus Interface 4. S
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Universal Serial Bus Interface endp
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16.6.14.2.4 Host System Error Unive
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Figure 16-61 shows the Endpoint Que
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Table 16-77 describes the multiple
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16.8 Device Operational Model Table
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Power Interruption When the Host Re
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16.8.2.2 Suspend/Resume This sectio
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Page 831 and 832:
Universal Serial Bus Interface Note
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16.8.3.5 Control Endpoint Operation
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Token Type Table 16-89. Control End
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Universal Serial Bus Interface must
Page 839 and 840:
NOTE After the acknowledge has occu
Page 841 and 842:
Universal Serial Bus Interface Comp
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Execution Order 1b USB Interrupt EN
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Universal Serial Bus Interface low-
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16.9.1.5.3 Asynchronous Transaction
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Figure 16-69 shows ULPI data transm
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Chapter 17 I 2 C Interfaces This ch
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sequence mode according to the BOOT
Page 857 and 858:
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17.3.1.3 I 2 Cn Control Register (I
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17.3.1.5 I 2 Cn Data Register (I2Cn
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17.4.3 Handshaking MPC8306 PowerQUI
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Master Xmit Generate STOP Write nex
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Chapter 18 DUART This chapter descr
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18.1.2 Modes of Operation The commu
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information about each register. Un
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Table 18-5 describes the UTHR. 18.3
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Table 18-9 describes the UIER field
Page 887 and 888:
Figure 18-8 shows the bits in the U
Page 889 and 890:
Table 18-14 describes the ULCR fiel
Page 891 and 892:
18.3.1.10 Line Status Registers (UL
Page 893 and 894:
18.3.1.12 Scratch Registers (USCR1
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18.4.3 Local Loopback Mode MPC8306
Page 899 and 900:
18.5 DUART Initialization/Applicati
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Chapter 19 Serial Peripheral Interf
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19.2.2 SPI Transmission and Recepti
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Serial Peripheral Interface Transmi
Page 907 and 908:
19.3.1 Overview Table 19-1 lists si
Page 909 and 910:
19.4.1 Register Descriptions This s
Page 911 and 912:
Serial Peripheral Interface Figure
Page 913 and 914:
Serial Peripheral Interface SPIM bi
Page 915 and 916:
19.4.1.6 SPI Receive Data Hold Regi
Page 917 and 918:
Chapter 20 JTAG/Testing Support 20.
Page 919 and 920:
TDO O JTAG test data output. JTAG/T
Page 921 and 922:
Chapter 21 General Purpose I/O (GPI
Page 923 and 924:
General Purpose I/O (GPIO) 0xD00 GP
Page 925 and 926:
21.3.4 GPIOn Interrupt Event Regist
Page 927 and 928:
Chapter 22 QUICC Engine Block on th
Page 929 and 930:
QUICC Engine Block on the MPC8306 a
Page 931 and 932:
Page 933 and 934:
22.2.1.5 System Interface—Arbitra
Page 935 and 936:
6 BER_1_MSK Mask bus error events.
Page 937 and 938:
Figure 22-7. DMA Command Queue QUIC
Page 939 and 940:
Table 22-6 describes the SDTAx fiel
Page 941 and 942:
Page 943 and 944:
Page 945 and 946:
Page 947 and 948:
22.2.1.7.6 Interrupt Vector Generat
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Page 951 and 952:
Page 953 and 954:
Table 22-14 defines the bit fields
Page 955 and 956:
Table 22-16 describes CIPXCC fields
Page 957 and 958:
22.2.1.8.8 QUICC Engine System Inte
Page 959 and 960:
Page 961 and 962:
22.2.1.8.13 QUICC Engine RISC Inter
Page 963 and 964:
22.2.2 Configuration - Parameter RA
Page 965 and 966:
22.2.2.5 QUICC Engine Microcode Rev
Page 967 and 968:
Table 22-25 shows the CEVTxxMR fiel
Page 969 and 970:
Page 971 and 972:
22.2.3.2 QUICC Engine Multiplexing
Page 973 and 974:
Appendix A Complete List of Configu
Page 975 and 976:
A.3 Watchdog Timer (WDT) A.4 Real T
Page 977 and 978:
Complete List of Configuration, Con
Page 979 and 980:
A.10 Reset Configuration A.11 Clock
Page 981 and 982:
Page 983 and 984:
Table A-16. DUART Registers (contin
Page 985 and 986:
A.18 Serial Peripheral Interface (S
Page 987 and 988:
Page 989 and 990:
0x180- 0x27F 0x280- 0x047F 0x480- 0
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