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Contents
Paragraph
Number Title
Chapter 20
JTAG/Testing Support
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual, Rev. 0
Page
Number
20.1 Overview........................................................................................................................ 20-1
20.2 JTAG Signals ................................................................................................................. 20-1
20.2.1 External Signal Descriptions ..................................................................................... 20-2
20.3 JTAG Registers and Scan Chains .................................................................................. 20-3
Chapter 21
General Purpose I/O (GPIO)
21.1 Introduction.................................................................................................................... 21-1
21.1.1 Overview.................................................................................................................... 21-1
21.1.2 Features...................................................................................................................... 21-1
21.2 External Signal Description ........................................................................................... 21-2
21.2.1 Signals Overview....................................................................................................... 21-2
21.3 Memory Map/Register Definition ................................................................................. 21-2
21.3.1 GPIOn Direction Register (GP1DIR–GP2DIR)........................................................ 21-3
21.3.2 GPIOn Open Drain Register (GP1ODR–GP2ODR) ................................................. 21-4
21.3.3 GPIOn Data Register (GP1DAT–GP2DAT).............................................................. 21-4
21.3.4 GPIOn Interrupt Event Register (GP1IER–GP2IER)................................................ 21-5
21.3.5 GPIOn Interrupt Mask Register (GP1IMR–GP2IMR).............................................. 21-5
21.3.6 GPIOn Interrupt Control Register (GP1ICR–GP2ICR) ............................................ 21-6
Chapter 22
QUICC Engine Block on the MPC8306 and MPC8306S
22.1 QUICC Engine Block .................................................................................................... 22-1
22.2 QUICC Engine Implementation Details for the MPC8306 and MPC8306S................. 22-3
22.2.1 System Interface ........................................................................................................ 22-5
22.2.2 Configuration – Parameter RAM............................................................................. 22-37
22.2.3 QUICC Engine Multiplexing and Timers................................................................ 22-42
22.2.4 UCC Ethernet (UEC)............................................................................................... 22-45
22.2.5 IEEE Standard 1588 Assist...................................................................................... 22-45
Appendix A
Complete List of Configuration, Control, and Status Registers
A.1 Local Access Windows.................................................................................................... 1-1
A.2 System Configuration Registers ...................................................................................... 1-2
A.3 Watchdog Timer (WDT).................................................................................................. 1-3
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