JOURACA_SP_2017

Optimizing System Design
Using SystemC and VHDL
Tristen Higginbotham
SystemC is a system design and implementation
language that is modeled after C++.
This language builds on the user's familiarity
of C++, allowing digital design to take
place at a relatively higher level with hardware
functionality being expressed by behavioral
constructs. JHDL, based on Java, is
another hardware description language
which allows for the utilization of objectoriented
style programming in circuit design.
Alternatively, VHDL is a commonly used
hardware description language which allows
the user to design circuitry more explicitly.
While these languages can be utilized to
produce similar systems, the complexity of
the resulting logic determines the optimal
design. The purpose of this research project
is to identify and analyze differences between
SystemC, JHDL, and VHDL implementations
through execution timing, complexity
comparisons, and analysis of resulting
chip space. Through this research, we
will be able to determine in what capacity
each language is most optimal, be it speed,
size, or simplicity of their respective products.
Department of Electrical Engineering
and Computer Engineering
Computer Science
Mentor: Dr. Todd Andel
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