S1D13806 TECHNICAL MANUAL

Page 30 Epson Research and Development
Vancouver Design Center
4.2.2 LCD Interface
Pin Name Type QFP Pin #
FPDAT[23:0] O
107-100,
91-90, 98-
93, 87-80
PFBGA
Pin #
C16, D14,
F12, E14,
D15, E16,
E15, G12,
G13, F15,
G16, H12,
G15, H13,
H14, J12,
J15, J14,
K13, K15,
K14, K12,
L15, L14
4.2.3 MediaPlug Interface
Table 4-3 : LCD Interface Pin Descriptions
Cell
RESET#
State
CO2 0
FPFRAME O 74 P16 CO2 0 Frame pulse
FPLINE O 75 N14 CO2 0 Line pulse
FPSHIFT O 78 M15 CO2 0 Shift clock
DRDY O 77 M14 CO2 0
Pin Name Type QFP Pin #
PFBGA
Pin #
Description
Panel data bus. Not all pins are used for some panels - see Table
4-10, “CPU Interface Pin Mapping,” on page 34 for details. Unused
pins are driven low.
This is a multi-purpose pin:
For TFT/D-TFD panels this is the display enable output (DRDY).
For passive LCD with Format 1 interface this is the 2nd Sh ift
Clock (FPSHIFT2).
For all other LCD panels this is the LCD backplane bias signal
(MOD).
See Table 4-11, “LCD Interface Pin Mapping,” on page 35 and
REG[030h] for details.
Table 4-4 : MediaPlug Pin Description
Cell
RESET#
State
VMP[7] O 131 E8 CO2 0 MediaPlug VMPLCTL pin.
VMP[6] I 130 B7 CD Hi-Z
VMP[5:2] IO 129-126
D8, A8, C8,
E9
C/TS2U 0 or Hi-Z
VMP[1] O 125 A9 CO2 0 MediaPlug VMPCLK pin.
VMP[0] O 124 D9 CO2 0 MediaPlug VMPCLKN pin.
Description
MediaPlug VMPRCTL pin.
Internal pull-down resistors (typical value of 50ΚΩ at 3.3V
respectively) pull the reset states to 0. External pull-up resistors can
be used to pull the reset states to 1.
MediaPlug VMPD[0:3] pins. See Section 17.3, “MediaPlug Interface
Pin Mapping” on page 188.
Internal pull-up resistors (typical value of 100ΚΩ at 3.3V respectively)
pull the reset states to 1. External pull-down resistors can be used to
pull the reset states to 0.
S1D13806 Hardware Functional Specification
X28B-A-001-11 Issue Date: 02/01/23