S1D13806 TECHNICAL MANUAL

Page 32 Epson Research and Development
Vancouver Design Center
4.2.6 Configuration
Pin Name Type QFP Pin #
CONF[7:0] I
138-142,
2-4
4.2.7 Miscellaneous
Pin Name Type QFP Pin #
PFBGA
Pin #
A5, B4, C5,
E6, C4, C1,
D3, F5
Table 4-7 : Configuration Pin Descriptions
Cell
RESET#
State
C Hi-Z
Table 4-8 : Miscellaneous Interface Pin Descriptions
PFBGA
Pin #
Cell
RESET#
State
Description
Input Configuration pin.
State of pins are latched at RESET# to configure S1D13806 -- Table
4.3, “Summary of Configuration Options,” on page 33 for details.
Description
CLKI I 66 T12 C Hi-Z
Input clock for the internal pixel clock (PCLK), memory clock
(MCLK), and MediaPlug clock.
CLKI2 I 64 M10 C Hi-Z Input clock for the internal pixel clock (PCLK) and MediaPlug clock.
CLKI3 I 62 N10 C Hi-Z
TESTEN I 5 E3 CD Hi-Z
Input clock for memory clock (MCLK) (Possible to use for PCLK and
MediaPlug clock.)
Test Enable. This pin should be connected to V SS for normal
operation.
DTESEN I 56 T9 C Hi-Z
Test Enable for embedded SDRAM. This pin should be connected to
VSS for normal operation.
TEST — 133 B6 — — Test Pin. This pin must be left unconnected and floating.
IOVDD P
1, 37, 73,
92, 109, 123
E4, N5,
M13, H16,
D12, B9
P — V DD for IO (IO V DD)
COREVDD P 27, 89, 122 L1, J16, C9 P — V DD for core (Core V DD )
AVDD P
110, 114,
116
A14, C12,
D11
P —
V DD for DAC (DAC V DD ). When the DAC is not used this pin must be
connected to DVDD.
DVDD P 38, 132 A7, T3 P — V DD for embedded SDRAM (SDRAM V DD )
VSS P
36, 59, 72,
79, 88, 99,
108, 121,
144
M4, M9,
N12, M16,
J13, F16,
E13, A10,
D5
P — V SS
AVSS P 111, 118 B13, B11 P — VSS for DAC (DAC VSS) DVSS P 58, 143 A3, R10 P — VSS for embedded SDRAM (SDRAM VSS) Reserved — 76 L12 -- — This pin must be left unconnected and floating.
S1D13806 Hardware Functional Specification
X28B-A-001-11 Issue Date: 02/01/23