10-Gigabit Ethernet Switch Performance Testing - Ixia

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What Are the Challenges in Processing Packets at 10G Rates? then examines the packet header and decides where to forward the packet. When multiple ingress ports contend for an egress port, congestion becomes the primary issue at the egress switch port and, depending on the architecture, may cause Head-of-Line blocking (HOL). HOL blocking occurs with input queuing, when a cell (a segmented packet to be transmitted across the backplane) has to be held up, thereby blocking the progress of any cells This section examines the most common stress points within a switch, and discusses conditions that might push them toward a strained state. Refer to Figure 2. Stress Point 1: Ingress packet buffer The ingress packet buffer is a temporary repository for arriving packets waiting to be processed by the packet processor. Depending on the architecture and efficiency of the packet processor, data in the packet buffer could build up, resulting in intermittent (poor) latency, jitter, packet loss, or even service outage. In most architectures, when packet buffers begin to fill beyond a preset threshold, the packet processor initiates flow control to the upstream MAC device, requesting it to stop passing packets. The MAC device then transmits a special packet requesting remote ports to delay sending packets for a period of time. This special packet is called a pause frame. This helps prevent buffer overflow, but it does not solve the packet loss problem completely. If the packet flow continues and the flow control signal is not removed by the packet processor before the MAC device’s buffer fills up, the MAC device will start dropping packets. Generally, the buffer in any part of the system can build up for two reasons: • Local or downstream devices are exceeding their allocated processing budget; or behind it, even if they could otherwise be switched. Some switch architectures also provide multicast packet replication. To get around packet replication issues, most modern switch fabrics now allow for an incoming packet to be broadcast to any number of egress ports. Typically, on the ingress and egress line cards, separate queues and scheduling disciplines are maintained for unicast and multicast traffic. • There is contention for resources — for instance, multiple ingress ports on a switch/router contending for an egress port. Buffer buildup can create a chain reaction, leading to unpredictable behavior in a switch or router. Another challenge in packet buffering for 10GE switches is dealing with back-to-back small packets. For example, at 10 Gbps speeds, arriving 64-byte packets must be deposited into buffer memory every 67 nanoseconds (ns), and departing packets must be retrieved from buffer memory every 67ns. Thus, to process a stream of back-to-back 64-byte packets, the packet buffer memory subsystem must support a write and a read every 67ns. Stress Point 2: Packet classification Packet classification is one of the most susceptible stress points. Classification maps information from the packet header to information stored in local tables maintained by a control plane processor (see "Stress Point 6: Control plane"). The packet processor parses various fields in the packet header to construct search keys. These keys are then used to address various tables. In most high-end architectures, Ternary Content Addressable Memory (TCAM) devices or equivalent technologies are used to map these keys to addresses, and are capable of holding millions of entries and 10-Gigabit Ethernet Switch Performance Testing Copyright © 2004, Ixia 11
performing key searches in a matter of few internal clock cycles. However, complex applications or routing protocols may require multiple key searches to drive a look-up result. Furthermore, separate classification sequences may be required to determine what to do with a packet. For example, the packet processor may perform an ACL look-up first to decide whether to forward or deny a packet, and then do a route look-up to decide where to forward it. It might also perform a flow control look-up to provide enhanced services. The required degree of packet parsing and processing is one of the main criteria that identifies the class of a switch/router. A simple Layer 2-3 switch only inspects the L2 header (i.e., MAC header, VLAN), and the L3 header (i.e., IPv4, IPv6), and, in some cases, performs limited flow classification. Complex packets might require the classification of multiple L2-L3 headers for a given packet. Packets of a given protocol may be encapsulated within one or more tunnels of varying protocols, as shown in Figure 3. For example, a system supporting IPv6 over GRE requires two Layer 3 headers (IPv4 and IPv6) in addition to the Layer 2 MAC addresses. A more complex example is a Layer 2 VPN Martini Draft IPv6 over GRE packet Dest MAC Dest MAC Src MAC Type Src MAC IPv4 header Ethernet over MPLS packet Type MPLS label GRE IPv6 header EXP S TTL Dest MAC packet with frames arriving over Ethernet in a wide range of dispositions, including IPv4 routing, MPLS switching or Ethernet bridging. Flow classification. In addition to complex packet classification, flow classification might be required to provide enhanced services and policies. Flow classification provides a level of granularity that allows policies to be established based on the applications. Any number of combinations of Layer 3 and Layer 4 information could be employed to define the QoS or security policies that are then enforced. A flow is a collection of one or more packet streams. In some classes of switches/ routers, in addition to packet classification, flow classifiers perform stateful analysis of packets within the packet streams. Flow classifiers track the protocol state of each flow as the connection develops. This makes it possible to track control connections on well-known ports that spawn data connections on ephemeral ports. This is important, since many protocols establish connections and negotiate services on well-known Transmission Control Protocol (TCP) ports and then establish another ephemeral port to transfer the data for the network session. TCP/UDP datagram Figure 3. Packets may be encapsulated in tunnels of varying protocols. 12 Copyright © 2004, Ixia 10-Gigabit Ethernet Switch Performance Testing Src MAC Type IPv4 header TCP/UDP datagram
Page 1 and 2: Enabling a Converged World 10-Giga
Page 3 and 4: Copyright © 1998-2004 Ixia. All ri
Page 5 and 6: 4 Copyright © 2004, Ixia 10-Gigabi
Page 7 and 8: 10-Gigabit Ethernet LAN The biggest
Page 9 and 10: What Happens to a Packet When It En
Page 11: Metering and statistics recording P
Page 15 and 16: Random Early Detection (RED) or Wei
Page 17 and 18: Developing the Right Test Methodolo
Page 19 and 20: Anticipating the behavior of the 10
Page 21 and 22: Ixia’s Test Solution Ixia provide
Page 23 and 24: Appendix: 10GE Testing Examples The
Page 25 and 26: 2. Testing for Latency: RFC 2544 La
Page 27 and 28: Methodology 1. Packets will be sent
Page 29 and 30: Results. The test results provide a
Page 31: Ternary Content Addressable Memory

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