10-Gigabit Ethernet Switch Performance Testing - Ixia

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What Is Inside a Multi-10GE Port Switch? Testing the new generation of 10GE switches requires a clear understanding of the various building blocks that make up a switch, and their interaction, to determine the various stress points within a switch and identify the weakest link in the chain. Figure 1 shows the major components of a 10GE switch, including the line card, the switch fabric card, and the controller card. The following subsections provide an overview of the 10GE switch/router components crucial to performance testing. Packet buffer The packet buffer is a temporary repository for arriving packets while they wait to be processed. Packet processing function The packet processor is an optimized ASIC or programmable device (Network Processing Unit, or NPU) for processing and forwarding packets in the data plane or fast path. It performs specific key tasks such as parsing the header, pattern matching or classification, table look-ups, packet modification, and packet forwarding, ideally at wire speed. Classification tables The classification table is a special memory used by the packet processor. It may contain the following databases: •The routing table determines where to route incoming packets. • Access Control Lists (ACLs) contain information to grant or deny permission to specific users or groups •The flow classification table contains information about a particular user or group of users, protocols, and applications. Flow identification information is used to determine QoS treatment, packet policing, and perflow queuing and billing. •The label table contains information about VLANs, stacked VLANs, MPLS labels, etc. Context memory Context memory contains instructions about whether to deny or forward packets, where to forward them, all the internal system headers needed to get a packet from an ingress to an egress port, and the external packet header (new MAC, IP, MPLS stacks, etc.). It also holds information relevant to metering the packet and other miscellaneous information about how to process a packet. Traffic management function The traffic management function is used to regulate the flow of traffic. It forwards traffic according to a user-defined set of rules pertaining to priority levels, latency and bandwidth guarantees, and congestion levels. It also provides the buffering required to work with any queuing mechanisms it uses to manage traffic flow across the switch fabric. It may also include the high-speed SERDES (serializer/deserializer) function used to connect to the switch fabric. Switch fabric The switch fabric provides data plane interconnection among all line cards in the system. The switch fabric typically employs a crossbar to move packets between its ingress and egress ports. An NxN crossbar switch fabric allows N line cards in a system to be interconnected in a chassis. This allows each slot to simultaneously send and receive traffic over the switch fabric. 10-Gigabit Ethernet Switch Performance Testing Copyright © 2004, Ixia 7
What Happens to a Packet When It Enters a 10GE Port? Figure 1. 10GE switch building blocks. This section provides a high-level walkthrough of the “life of a packet” as it goes from a port on an ingress line card through the switch fabric card and exits on an egress line card. Figure 2 shows the logical operation of various line cards in a multi-10GE port switch, and identifies the stress points (numbered red circles). Storing the packet When a packet arrives on a 10GE port, it is stored in ingress buffer memory while waiting to be processed by the packet processor. When the packet processor is ready, the packet header is copied into the packet processor memory for processing. Processing the packet The packet processor (ASIC or NPU) examines the packet to determine whether a packet should be filtered or forwarded. It makes this determination by parsing the packet header and then performing packet and flow classification. The classification process maps information extracted from the packet header to information stored in local tables maintained by the control plane processor. The information in the classification tables typically includes forwarding tables, routing tables, and profiles or rules for a given packet or flow, such as policies for ACLs, Quality of Service (QoS), and Class of Service (CoS). The classification typically points to many fragments of information about a packet. This information is usually saved in context memory and may contain instructions about whether to deny or forward the packet, where to forward it, all additional header information to get a packet from ingress to egress port, the new header used when it leaves the egress port (new MAC, IP, MPLS stacks, etc.), information relevant to policing the packet (see "Metering and statistics recording" below), and other information about how to process the packet. 8 Copyright © 2004, Ixia 10-Gigabit Ethernet Switch Performance Testing
Page 1 and 2: Enabling a Converged World 10-Giga
Page 3 and 4: Copyright © 1998-2004 Ixia. All ri
Page 5 and 6: 4 Copyright © 2004, Ixia 10-Gigabi
Page 7: 10-Gigabit Ethernet LAN The biggest
Page 11 and 12: Metering and statistics recording P
Page 13 and 14: performing key searches in a matter
Page 15 and 16: Random Early Detection (RED) or Wei
Page 17 and 18: Developing the Right Test Methodolo
Page 19 and 20: Anticipating the behavior of the 10
Page 21 and 22: Ixia’s Test Solution Ixia provide
Page 23 and 24: Appendix: 10GE Testing Examples The
Page 25 and 26: 2. Testing for Latency: RFC 2544 La
Page 27 and 28: Methodology 1. Packets will be sent
Page 29 and 30: Results. The test results provide a
Page 31: Ternary Content Addressable Memory

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