BajaPPC-750 User's Manual - Emerson Network Power
BajaPPC-750 User's Manual - Emerson Network Power
BajaPPC-750 User's Manual - Emerson Network Power
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Processor Initialization 3-3<br />
3.2.1 Hardware Implementation Dependent Register<br />
The Hardware Implementation Dependent Register, HID0, contains bits for<br />
CPU-specific features. Most of these bits are cleared on initial power-up of the<br />
<strong>BajaPPC</strong>-<strong>750</strong>. Please refer to the PPC<strong>750</strong> RISC Microprocessor User’s <strong>Manual</strong> for<br />
more detailed descriptions of the individual bit fields. The following register map<br />
summarizes HID0 for the PPC<strong>750</strong> CPU:<br />
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15<br />
EMCP DBP EBA EBD BCLK res. ECLK PAR DOZE NAP SLEEP DPM reserved NHR<br />
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31<br />
ICE DCE ILOCK DLOCK ICFI DCFI SPD IFEM SGE DCFA BTIC res. ABE BHT res.<br />
Register Map 3-2. PPC<strong>750</strong> Hardware Implementation Dependent, HID0<br />
EMCP Enable machine check pin. Initially enabled on the <strong>BajaPPC</strong>-<strong>750</strong>.<br />
DBP Enable bus address and data parity generation (in conjunction with EBA/<br />
EBD).<br />
EBA/EBD Bus address and data parity checking enables.<br />
BCLK Select bus clock for test clock pin.<br />
ECLK Enable external test clock pin.<br />
PAR Disable precharge of ARTRY* and shared signals.<br />
DOZE In doze mode the PLL, time base, and snooping are active.<br />
NAP In nap mode the PLL and time base are active.<br />
SLEEP In sleep mode no external clock is required.<br />
DPM Enable dynamic power management.<br />
NHR Not hard reset (software only). 0=hard reset, 1=no hard reset.<br />
ICE/DCE Instruction and data cache enables. The instruction cache is enabled on<br />
initial power-up.<br />
0002M621-15<br />
NOOP<br />
TI