BajaPPC-750 User's Manual - Emerson Network Power

3-10 BajaPPC-750: Central Processing Unit
3.7 JTAG/COP Interface
The JTAG/COP interface provides boundary-scan testing of the CPU and the
BajaPPC-750. This interface is compliant with IEEE 1149.1 interface standard.
JTAG interface signals are routed to header HDR1 (refer to the component map in
Fig. 2-5).
Table 3-6. JTAG/COP Interface Pin Assignments (HDR1)
Pin Signal Pin Signal
1 TDO 2 no connection
3 TDI 4 TRST*
5 no connection 6 +3.3V
7 TCK 8 no connection
9 TMS 10 no connection
11 SRESET* 12 GND
13 HRESET* 14 used as a keying pin
15 CKSTP_OUT* 16 GND
The signals for the JTAG/COP interface are defined as follows:
CKSTP_OUT* Checkstop Output. When asserted, this output signal indicates that the
CPU has detected a checkstop condition and has ceased operation. This
signal also drives the HALT LED on the BajaPPC-750 circuit board.
HRESET* Hard Reset. This input signal is used at power-up to reset the processor.
SRESET* Soft Reset. This input signal may initiate a warm reset.
TCK Test Clock Input. Scan data is latched at the rising edge of this signal.
TDI Test Data Input. This signal acts at the input port for scan instructions
and data.
TDO Test Data Output. This signal acts as the output port for scan instructions
and data.
TMS Test Mode Select. This input signal is the test access port (TAP) controller
mode signal.
TRST* Test Reset. This input signal resets the test access port.
May 2002