BajaPPC-750 User's Manual - Emerson Network Power
BajaPPC-750 User's Manual - Emerson Network Power
BajaPPC-750 User's Manual - Emerson Network Power
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Interrupt Handling 3-7<br />
3.4 Interrupt Handling<br />
The interrupt controller on the <strong>BajaPPC</strong>-<strong>750</strong> is a programmable logic device<br />
(PLD) that handles seven local interrupts and receives external interrupts from<br />
the counter/timers and PMC modules. (See Chapters 6 and 9 for additional information.)<br />
The interrupt controller drives the <strong>750</strong>_INT* interrupt input on the<br />
CPU. The interrupt controller’s registers are accessible through the MPC106 ROM<br />
interface.<br />
When an interrupt is pending, the CPU may read a unique vector from the controller<br />
at location FF9A,0060 16 or the current state of the interrupts from the<br />
Interrupt Status Register at FF9A,0070 16 . These 32-bit registers are connected to<br />
the most significant long word on the CPU bus.<br />
Table 3-5. Interrupt Vector Assignments<br />
Interrupt Source Mnemonic Priority Hex Vector<br />
Counter/Timer 2 CT2 Highest 0000,00B8<br />
Counter/Timer 1 CT1 0000,00B0<br />
Ethernet ETH 0000,00A8<br />
PMC Site 2 INTD* J2x INTD 0000,00A0<br />
PMC Site 2 INTC* J2x INTC 0000,0098<br />
PMC Site 2 INTB* J2x INTB 0000,0090<br />
PMC Site 2 INTA* J2x INTA 0000,0088<br />
PMC Site 1INTD* J1x INTD 0000,0080<br />
PMC Site 1 NTC* J1x INTC 0000,0078<br />
PMC Site 1INTB* J1x INTB 0000,0070<br />
PMC Site 1INTA* J1x INTA 0000,0068<br />
Universe output LINT7 0000,0060<br />
Universe output LINT6 0000,0058<br />
Universe output LINT5 0000,0050<br />
Universe output LINT4 0000,0048<br />
Universe output LINT3 0000,0040<br />
Universe output LINT2 0000,0038<br />
Universe output LINT1 0000,0030<br />
Universe output LINT0 0000,0028<br />
ISA bridge chip ISA INT 0000,0010<br />
Reset switch NMI 0000,0008<br />
None pending – Lowest 0000,0000<br />
0002M621-15