CBM Progress Report 2006 - GSI

Detector Developments CBM Progress Report 2006
Achievements of CMOS Pixel Sensors for the CBM Micro-Vertex Detector
S.Amar-Youcef 1 , A.Besson 2 , G.Claus 2 , M.Deveaux 1,2,3 , A.Dorokhov 2 , W.Dulinski 2 , S.Heini 2 ,
A.Himmi 2 , K.Jaaskelainen 2 , Ch.Müntz 1 , F.Rami 2 , J.Stroth 1 , I.Valin 2 , and M.Winter 2
1 J.W.Goethe Universität, Frankfurt; 2 IPHC and Université L.Pasteur, Strasbourg; 3 GSI, Darmstadt
It was already established that CMOS sensors provide
the single point resolution and reduced material budget required
for the ambitionned MVD vertexing performances.
Achieving these performances in the CBM running conditions
is however challenging, especially because of the
required radiation tolerance and read-out speed. Important
steps addressing these issues were made in 2006. Moreover,
a new generation of real size sensors was fabricated,
to be used for thinning and system integration studies [1].
Fast read-out architecture
The fast read-out architecture developped for the CBM
MVD extrapolates from the MIMOSA-8 prototype, designed
for the ILC vertex detector. The sensor includes
correlated double sampling micro-circuits and discriminators,
and delivers discriminated binary signals [2]. Its
single point resolution was evaluated in Summer 2006 at
the CERN-SPS. A resolution of 7 µm was found, i.e.
slightly better than the intrinsic resolution (∼ 7.2 µm) reflecting
the pixel pitch (25 µm). This result indicates that
integrated ADCs may not be mandatory to get a single
point resolution as small as ∼ 5 µm, provided the pixel
pitch is kept small enough (typically 18 µm). This perspective
coincides with the need for a small pitch in order
to enhance the sensor tolerance to bulk damage, by reducing
the distance the signal charges have to cross in order to
reach a sensing diode.
MIMOSA-8 was manufactured in TSMC 0.25 technology,
which features a 7 µm thick epitaxial layer. The
chip was translated in 2006 into the AMS 0.35 OPTO technology
(MIMOSA-16), where the layer is ∼ 11 µm thick.
Besides a larger signal amplitude, MIMOSA-16 also includes
other improvements: enhanced tolerance to ionising
radiation (MIMOSA-15 pixel architecture [2]), as well as
pixels incorporating high gain amplification micro-circuits.
Since it is not yet clear whether integrating an ADC at
the end of each column may be avoided, various ADC architectures
are being developed, in synergy with the ILC requirements.
The first ADC prototypes (5-bit Wilkinson and
4-bit successive-approximation ) designed at IPHC were
submitted to fabrication in Autumn 2006. Prominent design
challenges include compactness, aspect ratio, signal
processing speed and power dissipation.
Radiation tolerance
Radiation tolerance studies started with MIMOSA-15 in
2005 [2] were complemented in 2006 with ∼ 5 GeV/c e −
beam tests at DESY.
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A sensor exposed to an integrated dose of ∼ 1 MRad
(obtained with a 10 keV X-Ray source) was observed to
still exhibit a S/N ratio of 19 (it was 27 before irradiation),
and a detection efficiency of ∼ 99.9 % at a coolant temperature
of -20 ◦ C (180 µs integration time). These performances
validate the pixel architecture implemented against
parasitic leakage current generated by ionising radiation.
MIMOSA-15 chips irradiated with 1 MeV neutrons
were studied on the same beam. A sensor exposed
to ∼ 2·10 12 neq/cm 2 still exhibited a detection efficiency
above 99 % at a coolant temperature of -20 ◦ C. For a fluence
of ∼ 6·10 12 neq/cm 2 , the detection efficiency dropped
to ∼ 80 %. Given the available room from improvement,
these results indicate that fluences 10 13 neq/cm 2
per MVD layer are likely to be tolerable.
Improvements include pixel design optimisation and fabrication
process choices which reduce the diffusion path of
the signal electrons before reaching a sensing diode. Efforts
were made in 2006 towards this goal, on the one hand
by designing pixels featuring L-shaped sensing diodes and
on the other hand by fabricating a sensor in a BiCMOS
process featuring an epitaxial layer with a relatively high
resistivity expected to allow for substantial depletion.
New generation of real size sensors
The most attractive fabrication technology characterised
so far is the AMS-0.35 OPTO process. Excellent tracking
performances were obtained with 5 consecutive small prototypes
fabricated in this technology since late 2003, which
was chosen for the sensors currently developed for short
term tracking applications (STAR HFT, EUDET beam telescope).
The latter triggered an engineering run in 2006,
which was used to produce simultaneously a real size,
multi-purpose sensor, intended to equip a first generation
MVD demonstrator. The sensor, which features 256x256
pixels of 30 µm pitch, is read out in 1 ms. It was fabricated
in 2 different versions, one where the epitaxial layer
is ∼ 11 µm thick (default value) and one where it is expected
to be 16 µm (new commercial option). The engineering
run was also motivated by the possibility to study
the fabrication yield and to have a stock of real size sensors
available for thinning and system integration studies.
References
[1] M.Winter, “Status of CMOS sensor R&D”, talk presented at
the CBM collaboration meeting, Sept. 2005, GSI/Darmstadt;
[2] 2005 GSI Annual Report and references therein.