CBM Progress Report 2006 - GSI

FEE and DAQ CBM Progress Report 2006
Development of a test system for n-XYTER ASICs
A. Czermak 1 , P. Ku´smierski 2
1 Institute of Nuclear Physics (IFJ), PAN, Krakow, Poland; 2 Jagiellonian University, Krakow, Poland
We report on the progress at IFJ PAN with a readout system
for comprehensive tests of the n-XYTER ASIC. The
chip, developed by the DETNI Consortium and discussed
in [1], will be used for prototype detector developments in
the CBM experiment.
The SUCIMA DAQ board test system
The test system, which is based on the existing SUCIMA
Imager Module [2], has been adapted to operate the chip
and allows to perform a variety of laboratory measurements
with the ASIC, eventually being connected to silicon detectors.
A dedicated n-XYTER interface board has been
designed that matches geometrically and electrically the
SUCIMA data acquisition module. The SUCIMA board
is shown in Fig. 1 mounted on top of an ASIC interface
board carrying the 32-channel version of the 128-channel
n-XYTER chip, called MSGCROC.
Figure 1: SUCIMA DAQ module on MSGCROC board.
First results from the MSGCROC chip
We have developed the VHDL programs for the basic
FPGA logic on the DAQ board as well as the software
for the Graphical User Interface. In collaboration with
DETNI, the software has already been used for initial tests
of the MSGCROC chip, including data storage, performance
analysis and documentation of the test results. All
measurements have been performed at nominal 3.3 V supply
and nominal bias currents controlled by internal digitalto-analog
converters. The internal bias reference currents,
discrimination threshold voltage and various test modes in
the ASIC are set via the SUCIMA board and the I 2 C interface.
Test results for trigger efficiency versus thresholds
for different input charges are presented in Fig. 2, and pulse
waveforms recorded at the output of the slow shaper (with
gain set to 1) in Fig. 3.
The tests performed on the MSGCROC demonstrate correct
functionality of all building blocks of the ASIC. The
50
Figure 2: Trigger efficiencies (in arbitrary units) of all
MGCROC channels for different test pulses, as a function
of the adjusted threshold (in Volt).
Figure 3: Pulse waveforms at the output of the slow shaper.
analogue parameters, i.e. gain, noise and also matching
of these parameters are in agreement with the design
specifications. The critical digital circuits responsible
for data de-randomization and zero-suppressing token ring
based readout have been tested at a lower clock frequency
(64 MHz) than the nominal one (256 MHz). However,
there are no indications that the ASIC should not perform
correctly at higher clock frequencies.
Preparations for n-XYTER chip tests
In the near future, we will extend the test system to
operate the 128-channel n-XYTER ASIC: Several interface
boards have already been produced together with GSI.
The Krakow group will populate these interface cards with
components and will perform some initial tests. The boards
will then be sent to GSI for mounting the n-XYTER chips.
With the interface boards completed, both the n-XYTER
designers and the SUCIMA DAQ team will work together
on complete tests of the system and of the ASICs. Finally,
two or three SUCIMA DAQ board based test systems will
be available to interested CBM collaboration institutes, to
explore the n-XYTER chip and its possible applications.
References
[1] Chr.J. Schmidt et al., this report
[2] A. Czermak et al., Proc. 8th ICATPP, Villa Olmo, Como,
Italy, 6-10 October 2003.