CBM Progress Report 2006 - GSI
CBM Progress Report 2006 - GSI
CBM Progress Report 2006 - GSI
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<strong>CBM</strong> <strong>Progress</strong> <strong>Report</strong> <strong>2006</strong> FEE and DAQ<br />
Towards high count rate, data driven Silicon strip readout electronics for <strong>CBM</strong><br />
and other FAIR experiments ∗<br />
C. J. Schmidt 1,2 , K. Solv˚ag 1,3 , G. Modzel 2 , H. K. Soltveit 2 , and S. Löchner 1<br />
1 <strong>GSI</strong>, Darmstadt, Germany; 2 Phys. Inst., Heidelberg, Germany; 3 Inst. of Phys. and Techn., Bergen, Norway;<br />
Introduction<br />
<strong>CBM</strong> projects a large area multi station Silicon tracking<br />
station (STS) as one of its core detector systems. It will<br />
experience hit rates in the order of the ones targeted for<br />
LHC Silicon tracking systems. System- as well as physicslatencies<br />
impede the employment of complex tracking triggers<br />
like the one for open charm in a typical L1 trigger. No<br />
trigger information will be available in time to tag events<br />
of interest. Further, multi-event confluence in time must be<br />
considered typical rather than exceptional. This harsh environment<br />
not only poses tough demands on front-end detector<br />
and readout technology in terms of radiation hardness<br />
but also sets the stage to a novel, purely data driven readout<br />
architecture currently under development in the EU-FP6<br />
project DETNI 1 targeting thermal neutron scattering applications<br />
[1]. Such asynchronous, non triggered, high rates<br />
and self sparsifying front-end readout architecture cast in<br />
Silicon as a microchip is the current choice to cope with the<br />
projected challenges. <strong>CBM</strong> and <strong>GSI</strong> closely cooperate with<br />
DETNI and engaged in evaluating the first DETNI prototype<br />
microchip n-XYTER at the <strong>GSI</strong> detector lab. These<br />
studies on the 128 channel chip will then allow the development<br />
of an adapted, radiation hard, dedicated <strong>CBM</strong>-<br />
XYTER chip for the <strong>CBM</strong> Silicon Tracker System. The<br />
good adaptation to Silicon strip detectors together with the<br />
non-specialized readout has generated great interest with<br />
several major FAIR projects that see in this architecture a<br />
promising choice to satisfy their particular needs.<br />
Figure 1: The n-XYTER chip<br />
Data Driven Chip Architecture<br />
The n-XYTER is a 128 channel front-end mixed-signal<br />
ASIC design. Each channel consists of a preamplifier and<br />
two parallel pulse shapers, a fast one for timing and a slow<br />
∗ Work supported by EU-FP6 HADRONPHYSICS (see Annex) and<br />
EU-FP6 NMI3 DETNI<br />
1DETNI is a JRA of NMI-3 focussed upon neutron det. development<br />
49<br />
one for pulse height analysis. A discriminator on the fast<br />
channel will reset a peak detector on the slow channel in<br />
time that the signal height may be detected. Simultaneously<br />
it will trigger latching a time stamp with 1ns resolution<br />
that is used to tag the data. This asynchronous<br />
operation of the front-end together with the discriminator<br />
triggered data capture is termed in short as purely data<br />
driven front-end. For every channel, both, analogue pulse<br />
height and the digital time stamp, are then stored in FIFOs,<br />
where they will remain until readout. Data is read out of<br />
these FIFOs through a token ring structure, which will unprejudicedly<br />
read out whichever channel has data and skip<br />
non-hit channels. The chip is designed to be able to pump<br />
out data elements even at an average input rate of 32 ˙MHz,<br />
where momentary rates may statistically be fluctuating to<br />
even higher values. Each data element consists of a time<br />
stamp at 1ns resolution and an analogue pulse height to be<br />
digitized off chip.<br />
The n-XYTER realization shows noise figures of between<br />
850 and 1000 ENC on the fast channel (18 ns peaking time;<br />
depending upon polarity) at 30pF input capacitance, which<br />
is perfectly suited for MIP detection at standard Silicon<br />
thickness. The higher resolution slow channel with a peaking<br />
time of 140˙ns shows noise figures of about 600 ENC<br />
at 30pF input capacitance. The comparatively high capacitance<br />
targeted is at the expense of power. For the neutron<br />
application a non-issue, power is an important specification<br />
for a <strong>CBM</strong> version of the chip. A design to handle large capacitance<br />
specifications can either be used to handle longer<br />
strip detectors, otherwise it could be invested in long connecting<br />
wires from silicon to front-end allowing to remove<br />
necessary cooling infrastructure from within the detector.<br />
Towards the <strong>CBM</strong>-XYTER<br />
The n-XYTER is currently under careful investigation at<br />
the <strong>GSI</strong> detector lab. No flaws could be revealed so far.<br />
With the slow control operative, the architecture can now<br />
be explored in depth. After the current tests on isolated<br />
functionality, the chip will then be operated with an intelligent,<br />
more complex FPGA-based readout board. It will<br />
then finally be used to set up a Silicon strip detector test<br />
system. The analogue and digital tests as well as the detector<br />
system tests will be employed to formulate modifications<br />
that address the specific needs of <strong>CBM</strong>.<br />
References<br />
[1] NIM A, 568 (<strong>2006</strong>), 301-308