CBM Progress Report 2006 - GSI

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FEE and DAQ CBM Progress Report 2006 Development of building blocks for data driven architecture for the CBM microstrip detectors Eduard Atkin, Yuri Bocharov, Igor Ilyushchenko, Alexander Klyuev, Alexey Silaev, Andrey Simakov, Alexander Smirnov Department of Electronics, MEPhI Derandomiser architecture building blocks The analog derandomising architecture is expected to be a key one for CBM STS. For it therefore in 2006 there were designed and manufactured in the April 2006 run the several prototype blocks. Analog derandomizer block (42), the main idea of which was to develop a 4 channel fast analog FEE capable to process nanosecond signals deadtime-free by a fast cross-point switch and two output peak detectors. ADC building blocks have been designed to study a set associative multiplex architecture. The technique is based upon a spatial locality of adjacent ionized strips. Among those there were: Op amp (fully differential folded cascode OTA with switch capacitor feedback) with: gain – 75 dB, unity GB – 145 MHz, SR – 160 V/µs, settling time – 1 ns, supply – 0,5 mA ; Sample-hold circuit, based on the OTA; Multiphase generator; Test radiation tolerant MOS structures. A multipurpose test station for chips has been developed and used for lab tests. Fig.1 The derandomiser chip layout and the Test board with derandomiser chip Fig.2 Response of the comparators and cross-point switch The integrated charge sensitive amplifier In the frames of the R&D work there has been developed and tested an integrated circuit of CSA as a critical block of front-end electronics, responsible for accurate matching of strip sensors of different pitch Alexander Voronin, Victor Ejov, Andrey Fedenko SINP MSU 52 geometry (range of capacitances is up to 100pF) with read-out chain. The charge-sensitive preamplifier schematics is based on a classical folded cascode architecture with an additional nonlinear feedback network. This solution allows to combine the well-known advantages of the charge preamplifier configuration in terms of gain stability with the possibility of detector leakage current compensation. Specifications: – Dynamic range of a few MIPs; – Small signal – 7000 electrons per MIP; – Detector (sensor) capacitance in the range 30- 100 pF; – Max capacitive load – 100 fF (on-chip load); – Min load resistor – 10 kOhm; – Low power consumption of about 1 mW/channel; – Rise time (CSA output) – 10-200 ns; – Signal-to-noise ratio better than 10 for 1 MIP; – Number of channels – 8; – Detector coupling: a) AC – capacitor is on the detector or b) DC – CSA built-in leakage current compensation It should be possible to read-out Si-strip signals in both AC- and DC- coupling modes without saturation. CSA should withstand a maximum sensor leakage (dark) current as high as 1 µA; – Supply voltages – not more than ±3.3V (+1.8V typ.); – Minimal package height or caseless; – Minimal number of external components. Fig.3 The CSA chip layout and the Test board with CSA chip Fig.4 Response of the CSA
CBM Progress Report 2006 FEE and DAQ An ASIC based fast Preamplifier-Discriminator (PADI) for MRPCs ∗ M.Ciobanu 1,2 , A.Schüttauf 1 , E.Cordier 2 , N.Herrmann 2 , K.D.Hildenbrand 1 , Y.J.Kim 1 , M.Kiˇs 1 , P.Koczon 1 , Y.Leifels 1 , X.Lopez 1 , M.Marquardt 1 , J.Weinert 1 , and X.Zhang 1 1 GSI, Darmstadt, Germany; 2 Universität Heidelberg, Germany The use of conventional integrated circuits to process primary RPC signals has reached its limit with designs like FOPI’s 16 channel FEE5 [3]. To further reduce the price and power consumption per channel the natural way is a custom ASIC design. For this purpose the NINO architecture [1] used in the ALICE-ToF with its full differential structure offers a very attractive starting point for a new Preamplifier-Discriminator design. Figure 1: Asic Layout of the PADI chip with 3 channels Taking into account the existing ideas of time measurements with fast gas detectors with up to 100000 channels within the CBM-detector at the FAIR-facility of GSI, we started to investigate, within the European project JRA-12, the development a new 4 channel PADI- ASIC in CMOS 0.18 µm technology. This chip has the following key parameters: fully differential, 50 Ω input impedance, LVDS compatible output, preamplifier gain G ≥ 200, preamplifier bandwidth BW ≥ 400 MHz, peaking time tP ≤ 1ns, noise related to input σn ≤ 25µV RMS, comparator gain G ≥ 200, a DC feedback loop for offset and threshold stabilization and a threshold range related to the input of ∆UThr ∼0.5-20 mV. Based on these characteristics we designed a first version of the PADI-Chip (Fig. 1), with 3 channels in its first prototype. With the first delivered samples we have performed tests to check the basic functionality (connections, voltage, in/outputs of time and charge, thresholds). From these elementary tests we conclude that all channels are fully operational. Due to this very positive result we designed a ∗ work supported by JRA12 of EU/FP6 Hadronphysics (see annex), INTAS Ref.Nr. 03-54-3891 and German BMBF contract 06 HD190I. 53 PCB for the PADI-chip which is directly connected to our FOPI-digitizer TACQUILA3 [2]. Figure 2: First timing measurement of the PADI-chip together with the TACQUILA-card. A time-resolution σt ≤ 10 ps has been reached for a single channel. The combined setup (PADI-TACQUILA3) has a timing performance of σt ≤ 10 ps for pulser signals above 20 mV (see Fig 2.). In the following measurements we will map out the overall time resolution as a function of the amplitude. We will also compare time-over-threshold (ToT) to the direct charge measurement, to learn whether the ToT measurement is applicable for the walk correction. References [1] F.Anghinolfi, P.Jarron, A.N.Martemiyanov, E.Usenko, H.Wenninger, M.C.S.Williams and A.Zichichi Nucl. Inst. and Methods A, Vol. 533, Issues 1-2, 1 November 2004, 183-187 [2] K.Koch, H.Hardel, R.Schulze, E.Badura and J.Hoffmann IEEE Transactions on Nuclear Science, Vol. 52, No. 3, June 2005, 745-747 [3] M.Ciobanu a,b , A.Schüttauf a , E.Cordier b , N.Herrmann b , K.D.Hildenbrand a ,Y.J.Kim a , Y.Leifels a , M.Kis a , P.Koczon a , X.Lopez a , M.Marquardt a , M.Petrovici c , J.Weinert a ,X.Zhang a sub. to IEEE Transactions on Nuclear Science 2007
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CBM Progress Report 2006 1
Page 3 and 4:
Contents Preface i Overview 1 Simul
Page 5 and 6: CBM Progress Report 2006 Overview C
Page 7 and 8: CBM Progress Report 2006 Simulation
Page 31 and 32: CBM Progress Report 2006 Detector D
Page 53 and 54: CBM Progress Report 2006 FEE and DA
Page 55: CBM Progress Report 2006 FEE and DA
Page 59 and 60: CBM Progress Report 2006 FEE and DA
Page 61 and 62: CBM Progress Report 2006 Appendices
Page 63 and 64: Contacts CBM Spokesperson: Peter Se
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